AD6634BCSLASHPCB datasheet(48/52 Pages) AD

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AD6634

MICROPORT CONTROL

The AD6634 has an 8-bit microprocessor port and a serial control

port. The use of each of these ports is described separately below.

The interaction of the ports is then described. The microport

interface is a multimode interface that is designed to give flexibility

when dealing with the host processor. There are two modes

of bus operation: Intel Nonmultiplexed mode (INM), and

Motorola Nonmultiplexed mode (MNM). The mode is selected

based on host processor and which mode is best suited to that

processor. The microport has an 8-bit databus(D[7:0]), 3-bit

address bus(A[2:0]), three control pins lines (

CS, DS, or RD, RW

WR), and one status pin (DTACK or RDY). The functionality

of the control signals and status line changes slightly depending

upon the mode that is chosen. Refer to the timing diagrams and the

following descriptions for details on the operation of both modes.

External Memory Map

The External Memory Map is used to gain access to the channel

address space described previously. The 8-bit data and address

buses are used to this set of eight registers that can be seen in

Table XVI. These registers are collectively referred to as the

External Interface registers since they control all accesses to the

Channel Address space as well as input/output control registers.

The use of each of these individual registers is described in

detail. It should be noted that the Serial Control interface has

the same memory map as the microport interface and can carry

out the exact same functions, although at a slower rate.

Access Control Register (ACR)

The Access Control register serves to define the channel or

channels that receive an access from the microport or serial

port control.

Bit 7 of this register is the Auto-Increment bit. If this bit is a 1,

the CAR register described below will increment its value after

every access to the channel. This allows blocks of address space

such as coefficient memory to be initialized more efficiently.

Bit 6 of the register is the Broadcast bit and determines how

Bits 5–2 are interpreted. If Broadcast is 0, then Bits 5–2, which are

referred to as Instruction bits (Instruction[3:0]), are compared

with the CHIP_ID[3:0] pins. The instruction that matches the

CHIP_ID[3:0] pins will determine the access. This allows up to

16 chips to be connected to the same port and memory mapped

without external logic. This also allows the same serial port of a

host processor to configure up to 16 chips. If the Broadcast bit is

high, the Instruction[3:0] word allows multiple AD6634 channels

and/or chips to be simultaneously configured independent of the

CHIP_ID[3:0] pins. There are 10 possible instructions defined

in Table XVI. This is useful for smart antenna systems, where

multiple channels listing to a single antenna or carrier can be

configured simultaneously. The x(s) in the table represent don’t

cares in the digital decoding.

Table XVI. External Memory Map

A[2:0]

Name

Comment

111

Access Control Register (ACR)

Auto Increment

Broadcast

5–2:

Instruction[3:0]

1–0:

A[9:8]

110

Channel Address Register (CAR)

7–0:

A[7:0]

101

SOFT_SYNC Control Register (Write Only)

PN_EN

Test_MUX_Select

Hop

Start

SYNC D

SYNC C

SYNC B

SYNC A

100

PIN_SYNC Control Register (Write Only)

Toggle IEN for BIST

First SYNC Only

Hop_En

Start_En

SYNC_EN D

SYNC_EN C

SYNC_EN B

SYNC_EN A

011

SLEEP (Write Only)

7–6:

Reserved

Access Input/Output Control Registers

Reserved low

SLEEP 3

SLEEP 2

SLEEP 1

SLEEP 0

010

Data Register 2 (DR2)

7–4:

Reserved

3–0:

D[19:16]

001

Data Register 1 (DR1)

15–8: D[15:8]

000

Data Register 0 (DR0)

7–0:

D[7:0]

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