AD6634BCSLASHPCB datasheet(33/52 Pages) AD

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AD6634

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4. Set the Start on Pin Sync bit and the appropriate Sync Pin

Enable high (Ext Address 4 ) (A, B, C, or D).

5. When the Sync pin is sampled high by the AD6634 CLK, this

enables the count down of the Start Update Hold-Off Counter.

The counter is clocked with the AD6634 CLK signal. When it

reaches a count of 1, the Sleep bit of the appropriate channel(s)

is set low to activate the channel(s).

Hop

Hop is a jump from one NCO frequency to a new NCO

frequency. This change in frequency can be synchronized via

microprocessor control (Soft Sync) or an external Sync signal

(PIN Sync) as described below.

To set the NCO frequency without synchronization the following

method should be used.

Set Freq No Hop

1. Set the NCO Freq Hold-Off counter to 0.

2. Load the appropriate NCO frequency. The new frequency

will be immediately loaded to the NCO.

Hop with Soft Sync

The AD6634 includes the ability to synchronize a change in NCO

frequency of multiple channels or chips under microprocessor

control. The NCO Freq Hold-Off counter (0x84) in conjunction

with the Hop bit and the Sync bit (Ext Address 4) allow this

synchronization. Basically the NCO Freq Hold-Off counter

delays the new frequency from being loaded into the NCO by

its value (number of AD6634 CLKs). The following method is

used to synchronize a hop in frequency of multiple channels via

microprocessor control.

1. Note that the time from when DTACK (Pin 57) goes high to

when the NCO begins processing data is the contents of the

NCO Freq Hold-Off counter (0x84) + 7 master clock cycles.

2. Write the NCO Freq Hold-Off (0x84) counter to the appro-

priate value (greater than 1 and less then 2

16–1).

3. Write the NCO Frequency register(s) to the new desired

frequency.

4. Write the Hop bit and the Sync(s) bit high (Ext Address 4).

5. This starts the NCO Freq Hold-Off counter counting down.

The counter is clocked with the AD6634 CLK signal. When

it reaches a count of 1, the new frequency is loaded into

the NCO.

Hop with Pin Sync

The AD6634 include four Sync pins to provide the most accu-

rate synchronization, especially between multiple AD6634s.

Synchronization of hopping to a new NCO frequency with an

external signal is accomplished with the following method.

1. Note that the time from when the SYNC pin goes high to

when the NCO begins processing data is the contents of the

NCO Freq Hold-Off counter (0x84) + 5 master clock cycles.

2. Write the NCO Freq Hold-Off counter(s) (0x84) to the

appropriate value (greater than 1 and less than 2

16–1).

3. Write the NCO Frequency register(s) to the new desired

frequency.

4. Set the Hop on Pin Sync bit and the appropriate Sync Pin

Enable high.

5. When the selected Sync pin is sampled high by the AD6634

CLK, this enables the countdown of the NCO Freq Hold-Off

counter. The counter is clocked with the AD6634 CLK signal.

When it reaches a count of 1, the new frequency is loaded

into the NCO.

PARALLEL OUTPUT PORTS

The AD6634 incorporates two independent 16-bit parallel ports

for output data transfer. Both parallel ports share pins and internal

mux circuitry. A single parallel port and a single Link Port can

be used simultaneously, but only if they do not share the same

data path; the two possible choices are Parallel Port A with

Link Port B, or Parallel Port B with Link Port A. Figure 35

presents a simplified block diagram showing the AD6634’s output

data routing configuration.

OUTPUT PORT A

PARALLEL PORT A

LINK PORT A

OUTPUT PORT B

PARALLEL PORT B

LINK PORT B

Figure 35. Output Port Data Routing

Parallel port configuration is specified by accessing Port Control

respectively. Port clock Master/Slave mode (described later) is

configured using the Port Clock Control register at address

0x1E. Note that to access these registers, Bit 5 (Access Port

Control Registers) of external address 3 (SLEEP register) must

be set. The address is then selected by programming the CAR

The parallel ports are enabled by setting Bit 7 of the Link Control

registers at addresses 0x1B and 0x1D for ports A and B,

respectively.

Each parallel port is capable of operating in either Channel mode

or AGC mode. Each mode is described in detail below.

Channel Mode

Parallel port Channel mode is selected by setting Bit 0 of addresses

0x1B and 0x1D for parallel ports A and B, respectively. In

Channel mode, I and Q words from each channel is directed to

the parallel port, bypassing the AGC. The specific channels

output by the port are selected by setting Bits 1 through 4 of

Parallel Port Control Register 0x1A (port A) and 0x1C (port B).

Channel mode provides two data formats. Each format requires a

different number of parallel port clock (PCLK) cycles to complete

the transfer of data. In each case, each data element is trans-

ferred during one PCLK cycle. See Figures 36 and 37, which

present Channel mode parallel port timing.

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