AD6634BCSLASHPCB datasheet(37/52 Pages) AD

37 / 52 page

REV. 0

AD6634

–37–

0x80: Channel Sleep Register

This register contains the SLEEP bit for the channel. When this

bit is high, the channel is placed in a low power state. When this

bit is low, the channel processes data. This bit can also be set by

accessing the SLEEP register at external address 3. When the

External SLEEP register is accessed, all four channels are

accessed simultaneously and the SLEEP bits of the channels

are set appropriately.

0x81: Soft_SYNC Register

This register is used to initiate SYNC events through the

microport. If the Hop bit is written high, the Hop Hold-Off

Counter at address 0x84 is loaded and begins to count down.

When this value reaches 1, the NCO Frequency register used by

the NCO accumulator is loaded with the data from channel

addresses 0x85 and 0x86. When the Start bit is set high, the

Start Hold-Off Counter is loaded with the value at address

0x83 and begins to count down. When this value hits 1, the Sleep

bit in address 0x80 is dropped low and the channel is started.

0x82: Pin_SYNC Register

This register is used to control the functionality of the SYNC

pins. Any of the four SYNC pins can be chosen and monitored

by the channel. The channel can be configured to initiate either

a Start or Hop SYNC event by setting the Hop or Start bit high.

These bits function as enables so that when a SYNC pulse

occurs, either the Start or Hop Hold-Off Counters are activated

in the same manner as with a Soft_SYNC.

0x83: Start Hold-Off Counter

The Start Hold-Off Counter is loaded with the value written to

this address when a Start_Sync is initiated. It can be initiated

by either a Soft_SYNC or Pin_SYNC. The counter begins

decrementing and when it reaches a value of 1, the channel is

brought out of SLEEP and begins processing data. If the channel

is already running, the phase of the filters is adjusted such that

multiple AD6634s can be synchronized. A periodic pulse on the

SYNC pin can be used in this way to adjust the timing of the filters with

the resolution of the ADC sample clock. If this register is written

to a 1, the Start will occur immediately when the SYNC comes

into the channel. If it is written to a 0, no SYNC will occur.

0x84: NCO Frequency Hold-Off Counter

The NCO Frequency Hold-Off Counter is loaded with the value

written to this address when either a Soft_SYNC or Pin_SYNC

comes into the channel. The counter begins counting down so

that when it reaches 1, the NCO frequency word is updated

with the values of addresses 0x85 and 0x86. This is known as a

Hop or Hop_SYNC. If this register is written to a 1, the NCO

Frequency will be updated immediately when the SYNC

comes into the channel. If it is written to a 0, no HOP will

occur. NCO HOPs can be either phase continuous or nonphase

continuous, depending upon the state of Bit 3 of the NCO

control register at channel address 0x88. When this bit is low,

the phase accumulator of the NCO is not cleared but starts to

add the new NCO frequency word to the accumulator as soon as

the SYNC occurs. If this bit is high, the phase accumulator of

the NCO is cleared to 0 and the new word is then accumulated.

0x85: NCO Frequency Register 0

This register represents the 16 LSBs of the NCO Frequency

word. These bits are shadowed and are not updated to the regis-

ter used for the processing until the channel is either brought

out of SLEEP or a Soft_SYNC or Pin_SYNC has been issued.

In the latter two cases, the register is updated when the Frequency

Table X. Channel Address Memory Map

Channel

Bit

Address

Width

Comments

00–7F

Coefficient Memory (CMEM)

128

× 20-Bit Memory

CHANNEL SLEEP

0: SLEEP Bit from EXT_ADDRESS 3

Soft_Sync Control Register

1: Hop

0: Start

Pin_SYNC Control Register

2: First SYNC Only

1: Hop_En

0: Start_En

Start Hold-Off Counter

Start Hold-Off Value

NCO Frequency Hold-Off Counter

NCO_FREQ Hold-Off Value

NCO Frequency Register 0

NCO_FREQ[15:0]

NCO Frequency Register 1

NCO_FREQ[31:16]

NCO Phase Offset Register

NCO_PHASE[15:0]

NCO Control Register

8–7: SYNC Input Select[1:0]

6: WB Input Select B/A

5–4: Input Enable Control

11: Clock on IEN Transition to Low

10: Clock on IENTransition to High

01: Clock on IEN High

00: Mask on IEN Low

3: Clear Phase Accumulator on HOP

2: Amplitude Dither

1: Phase Dither

0: Bypass (A-Input

→ I-Path, B → Q)

89–8F

Unused

AD6634BC/PCB датащи(PDF) 37 Page - Analog Devices

AD6634BC/PCB датащи(HTML) 37 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

датащи скачать

ссылки URL