 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
TMS570LS1114 датащи(PDF) 90 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TMS570LS1114 датащи(HTML) 90 Page - Texas Instruments |
|
|
90 / 169 page  TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.15 Vectored Interrupt Manager The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow of program execution. Normally, these events require a timely response from the central processing unit (CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to an interrupt service routine (ISR). 6.15.1 VIM Features The VIM module has the following features: • Supports 128 interrupt channels. – Provides programmable priority and enable for interrupt request lines. • Provides a direct hardware dispatch mechanism for fastest IRQ dispatch. • Provides two software dispatch mechanisms when the CPU VIC port is not used. – Index interrupt – Register vectored interrupt • Parity protected vector interrupt table against soft errors. 6.15.2 Interrupt Request Assignments Table 6-31. Interrupt Request Assignments Modules Interrupt Sources Default VIM Interrupt Channel ESM ESM High level interrupt (NMI) 0 Reserved Reserved 1 RTI RTI compare interrupt 0 2 RTI RTI compare interrupt 1 3 RTI RTI compare interrupt 2 4 RTI RTI compare interrupt 3 5 RTI RTI overflow interrupt 0 6 RTI RTI overflow interrupt 1 7 RTI RTI timebase interrupt 8 GIO GIO interrupt A 9 N2HET1 N2HET1 level 0 interrupt 10 HTU1 HTU1 level 0 interrupt 11 MIBSPI1 MIBSPI1 level 0 interrupt 12 LIN LIN level 0 interrupt 13 MIBADC1 MIBADC1 event group interrupt 14 MIBADC1 MIBADC1 sw group 1 interrupt 15 DCAN1 DCAN1 level 0 interrupt 16 SPI2 SPI2 level 0 interrupt 17 Reserved Reserved 18 CRC CRC Interrupt 19 ESM ESM Low level interrupt 20 SYSTEM Software interrupt (SSI) 21 CPU PMU Interrupt 22 GIO GIO interrupt B 23 N2HET1 N2HET1 level 1 interrupt 24 HTU1 HTU1 level 1 interrupt 25 MIBSPI1 MIBSPI1 level 1 interrupt 26 90 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
