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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS570LS1114 датащи(PDF) 65 Page - Texas Instruments |
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TMS570LS1114 датащи(HTML) 65 Page - Texas Instruments |
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65 / 169 page  TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.6.3 Clock Test Mode The RM4x platform architecture defines a special mode that allows various clock signals to be brought out on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is very useful for debugging purposes and can be configured through the CLKTEST register in the system module. Table 6-14. Clock Test Mode Options SEL_ECP_PIN SEL_GIO_PIN = SIGNAL ON ECLK = SIGNAL ON N2HET1[12] CLKTEST[3-0] CLKTEST[11-8] 0000 Oscillator 0000 Oscillator Valid Status 0001 Main PLL free-running clock output 0001 Main PLL Valid status 0010 Reserved 0010 Reserved 0011 EXTCLKIN1 0011 Reserved 0100 LFLPO 0100 Reserved 0101 HFLPO 0101 HFLPO Valid status 0110 Secondary PLL free-running clock output 0110 Secondary PLL Valid Status 0111 EXTCLKIN2 0111 Reserved 1000 GCLK 1000 LFLPO 1001 RTI Base 1001 Oscillator Valid status 1010 Reserved 1010 Oscillator Valid status 1011 VCLKA1 1011 Oscillator Valid status 1100 VCLKA2 1100 Oscillator Valid status 1101 Reserved 1101 Reserved 1110 VCLKA4_DIVR 1110 VCLKA4_S 1111 Reserved 1111 Oscillator Valid status Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications 65 Submit Documentation Feedback Product Folder Links: TMS570LS1114 |
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