TMS570LS1114 datasheet(74/169 Pages) TI1

74 / 169 page

TMS570LS1114

SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015

www.ti.com

Table 6-21. Master / Slave Access Matrix

MASTERS

ACCESS MODE

SLAVES ON MAIN SCR

Flash Module

Non-CPU

CRC

EMIF Slave

Peripheral

Bus2 Interface:

Accesses to

Interface

Control

OTP, ECC, Bank

Program Flash

Registers, All

and CPU Data

Peripheral

RAM

Memories, And

All System

Module Control

Registers And

Memories

CPU READ

User/Privilege

Yes

CPU WRITE

User/Privilege

Yes

DMA

User

Yes

POM

User

Yes

DAP

Privilege

Yes

HTU1

Privilege

Yes

HTU2

Privilege

Yes

6.9.5

Special Notes on Accesses to Certain Slaves

Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU

(master id = 1). The other masters can only read from these registers.

A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.

The device contains dedicated logic to generate a bus error response on any access to a module that is in

a power domain that has been turned OFF.

6.9.6

Parameter Overlay Module (POM) Considerations

•

The POM can map onto up to 8MB of the internal or external memory space. The starting address and the size of

the memory overlay are configurable through the POM control registers. Care must be taken to ensure that the

overlay is mapped on to available memory.

•

ECC must be disabled by software through CP15 in case POM overlay is enabled; otherwise ECC errors will be

generated.

•

POM overlay must not be enabled when the flash and internal RAM memories are swapped through the MEM

SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).

•

When POM is used to overlay the flash on to internal or external RAM, there is a bus contention possibility when

another master accesses the TCM flash. This results in a system hang.

–

The POM implements a timeout feature to detect this exact scenario. The timeout needs to be enabled

whenever POM overlay is enabled.

–

The timeout can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global Control

–

In case a read request by the POM cannot be completed within 32 HCLK cycles, the timeout (TO) flag is set in

the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is generated to the CPU. This can

be a prefetch abort for an instruction fetch or a data abort for a data fetch.

–

The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM is set. If so, then

the application can assume that the timeout is caused by a bus contention between the POM transaction and

another master accessing the same memory region. The abort handlers need to clear the TO flag, so that any

further aborts are not misinterpreted as having been caused due to a timeout from the POM.

System Information and Electrical Specifications

Submit Documentation Feedback

Product Folder Links: TMS570LS1114

TMS570LS1114 датащи(PDF) 74 Page - Texas Instruments

TMS570LS1114 датащи(HTML) 74 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL