TMS570LS1114 datasheet(52/169 Pages) TI1

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TMS570LS1114

SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015

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6.3

Power Sequencing and Power On Reset

6.3.1

Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-

up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for

more details), core voltage rising above the minimum core supply threshold and the release of power-on

reset. The high frequency oscillator will start up first and its amplitude will grow to an acceptable level. The

oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The

different supplies to the device can be powered up in any order.

The device goes through the following sequential phases during power up.

Table 6-3. Power-Up Phases

Oscillator start-up and validity check

1032 oscillator cycles

eFuse autoload

1160 oscillator cycles

Flash pump power-up

688 oscillator cycles

Flash bank power-up

617 oscillator cycles

Total

3497 oscillator cycles

The CPU reset is released at the end of the above sequence and fetches the first instruction from address

0x00000000.

6.3.2

Power-Down Sequence

The different supplies to the device can be powered down in any order.

6.3.3

Power-On Reset: nPORRST

This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core

supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an

internal pulldown.

6.3.3.1

nPORRST Electrical and Timing Requirements

Table 6-4. Electrical Requirements for nPORRST

NO Parameter

MIN

MAX

Unit

VCCPORL

VCC low supply level when nPORRST must be active during power-

0.5

VCCPORH

VCC high supply level when nPORRST must remain active during

1.14

power-up and become active during power down

VCCIOPORL

VCCIO / VCCP low supply level when nPORRST must be active during

1.1

power-up

VCCIOPORH

VCCIO / VCCP high supply level when nPORRST must remain active

3.0

during power-up and become active during power down

VIL(PORRST)

Low-level input voltage of nPORRST VCCIO > 2.5V

0.2 * VCCIO

Low-level input voltage of nPORRST VCCIO < 2.5V

0.5

tsu(PORRST)

Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL

during power-up

th(PORRST)

Hold time, nPORRST active after VCC > VCCPORH

tsu(PORRST)

Setup time, nPORRST active before VCC < VCCPORH during power

µs

down

th(PORRST)

Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH

th(PORRST)

Hold time, nPORRST active after VCC < VCCPORL

System Information and Electrical Specifications

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