TMS570LS1114 datasheet(3/169 Pages) TI1

3 / 169 page

TMS570LS1114

www.ti.com

SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015

The device has two 12-bit-resolution MibADCs with 24 total inputs and 64 words of parity-protected buffer

RAM each. The MibADC channels can be converted individually or can be grouped by software for

sequential conversion sequences. Sixteen inputs are shared between the two MibADCs. Each MibADC

supports three separate groupings of channels. Each group can be converted once when triggered or

configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility

with older devices or faster conversion time is desired. MibADC1 also supports the use of external analog

multiplexers.

The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three

DCANs, and one I2C. The SPI provides a convenient method of serial high-speed communications

between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can

be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN

supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol

that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The

DCAN is ideal for systems operating in noisy and harsh environments (for example, automotive and

industrial fields) that require reliable serial communication or multiplexed wiring.

The I2C module is a multimaster communication module providing an interface between the

microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100

and 400 Kbps.

A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external

frequency reference to a higher frequency for internal use. The Global Clock Module (GCM) manages the

mapping between the available clock sources and the device clock domains.

The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous

external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral

interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of

the device operating frequency.

The Direct Memory Access (DMA) controller has 16 channels, 32 control packets, and parity protection on

its memory. An MPU is built into the DMA to protect memory against erroneous transfers.

The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt or

external error pin (ball) is triggered when a fault is detected. The nERROR terminal can be monitored

externally as an indicator of a fault condition in the microcontroller.

The External Memory Interface (EMIF) provides a memory extension to asynchronous and synchronous

memories or other slave devices.

A Parameter Overlay Module (POM) enhances the calibration capabilities of application code. The POM

can reroute flash accesses to internal memory or to the EMIF, thus avoiding the reprogramming steps

necessary for parameter updates in flash.

With integrated safety features and a wide choice of communication and control peripherals, the

TMS570LS1114 device is an ideal solution for high-performance real-time control applications with safety-

critical requirements.

Table 1-1. Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE

TMS570LS1114ZWT

NFBGA (337)

16.0 mm × 16.0 mm

TMS570LS1114PGE

LQFP (144)

20.0 mm × 20.0 mm

(1)

For more information, see Section 9, Mechanical Packaging and Orderable Information.

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