TMS570LS1114 datasheet(47/169 Pages) TI1

47 / 169 page

VCCIO

VIH

VIL

Input

tpw

VIL

TMS570LS1114

www.ti.com

SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015

Table 5-5. Selectable 8 mA/2 mA Control (continued)

Signal

Control Bit

Address

8 mA

2 mA

SPI2SOMI

SPI2PC9[11](1)

0xFFF7 F668

(1)

Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these two bits

differ, SPI2PC9[11] determines the drive strength.

5.11 Input Timings

Figure 5-2. TTL-Level Inputs

Table 5-6. Timing Requirements for Inputs(1)

Parameter

MIN

MAX

Unit

tpw

Input minimum pulse width

tc(VCLK) + 10

(2)

tin_slew

Time for input signal to go from VIL to VIH or from VIH to VIL

(1)

tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK)

(2)

The timing shown above is only valid for pin used in general-purpose input mode.

5.12 Output Timings

Table 5-7. Switching Characteristics for Output Timings versus Load Capacitance ©L)

Parameter

MIN

MAX

Unit

Rise time, tr

8 mA low EMI pins

CL = 15 pF

2.5

(see Table 5-4)

CL = 50 pF

CL = 100 pF

7.2

CL = 150 pF

12.5

Fall time, tf

CL = 15 pF

2.5

CL = 50 pF

CL = 100 pF

7.2

CL = 150 pF

12.5

Rise time, tr

4 mA low EMI pins

CL = 15 pF

5.6

(see Table 5-4)

CL = 50 pF

10.4

CL = 100 pF

16.8

CL = 150 pF

23.2

Fall time, tf

CL = 15 pF

5.6

CL= 50 pF

10.4

CL = 100 pF

16.8

CL = 150 pF

23.2

Specifications

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