AD6635BBSLASHPCB datasheet(26/60 Pages) AD

26 / 60 page

REV. 0

–26–

AD6635

IN13

IN2

IN1

IN0

IEN

D10 (MSB)

D0 (LSB)

AD6600

AD6635

EXP1

RSSI1

EXP2

RSSI2

EXP0

RSSI0

AB_OUT

Figure 28. Typical Interconnection of the AD6600

Gain-Ranging ADC and the AD6635.

NUMERICALLY CONTROLLED OSCILLATOR

Frequency Translation

This processing stage comprises a digital tuner consisting of two

multipliers and a 32-bit complex NCO. Each channel of the

AD6635 has an independent NCO. The NCO serves as a quadra-

ture local oscillator capable of producing an NCO frequency

between –CLK/2 and +CLK/2 with a resolution of CLK/2

32 in the

complex mode. The worst-case spurious signal from the NCO is

better than –100 dBc for all output frequencies.

The NCO frequency value in registers 0x85 and 0x86 are inter-

preted as a 32-bit unsigned integer. The NCO frequency is

calculated using the equation below.

NCO FREQ

CLKn

CHANNEL

mod

=¥

ËÁ

¯˜

where NCO_FREQ is the 32-bit integer (registers 0x85 and

0x86) that the user needs to set in order to tune to a desired

frequency fCHANNEL, and CLKn is the AD6635 master clock rate

or Input data rate, depending on the Input Enable mode used.

See the Input Enable Control section to determine when it is

CLK and when it is Input data rate. For Channels 0 through 3

use CLK0, and for Channels 4 through 7 use CLK1.

“mod” is similar to the remainder function. For example if

fCHANNEL = 220 MHz and CLK = 80 MHz, then mod(220/80,1)

= mod(2.75,1) = 0.75.

But for negative frequencies, for example,

mod(–220/80,1) = mod(–1.75,1) = 0.25.

This definition works if NCO_FREQ register is treated as a

signed number.

NCO Frequency Holdoff Register

When the NCO frequency registers are written, data is actually

passed to a shadow register. Data may be moved to the main

registers by one of two methods: when the channel comes out of

sleep mode, or when a SYNC hop occurs. In either event, a

counter can be loaded with the NCO Frequency Holdoff regis-

ter value. The 16-bit unsigned integer counter (0x84) starts

counting down, clocked by the Master clock, and when it reaches

zero, the new frequency value in the shadow register is written

to the NCO frequency register. The NCO could also be set up

to SYNC immediately, in which case the Frequency Holdoff

counter is bypassed (by writing a value of 1) and new frequency

values are updated immediately. If a zero is written, then SYNC

will never occur.

Phase Offset

The Phase Offset register (0x87) adds an offset to the phase

accumulator of the NCO. The NCO phase accumulator starts

with the value in this register in the event of a START SYNC.

This is a 16-bit register and is interpreted as a 16-bit unsigned

integer. A 0x0000 in this register corresponds to a 0 radian

offset, and a 0xFFFF corresponds to an offset of 2

¥ (1 – 1/(216))

radians. This register allows multiple NCOs to be synchronized to

produce sine waves with a known and steady phase difference.

NCO Control Register

The NCO control register located at 0x88 is used to configure

the features of the NCO. These are controlled on a per channel

basis and are described below.

Bypass

The NCO in the front end of the AD6635 can be bypassed.

Bypass mode is enabled by setting Bit 0 of 0x88 high. When the

NCO is bypassed, down conversion is not performed and the

AD6635 channel functions simply as a real filter on complex

data. This is useful for a baseband sampling application where

the A input is connected to the I signal path within the filter,

and the B input is connected to the Q signal path for Channels 0

through 3. Similarly, input C is connected to I signal path and

input D to Q signal path for Channels 4 through 7. This may be

desired if the digitized signal has already been converted to

baseband in prior analog stages or by other digital preprocessing.

Phase Dither

The AD6635 provides a phase dither option for improving the

spurious performance of the NCO. Phase dither is enabled by

setting Bit 1 of the NCO control register. When phase dither is

enabled by setting this bit high, spurs due to phase truncation in

the NCO are randomized. The energy from these spurs is

spread into the noise floor and spurious-free dynamic range is

increased at the expense of very slight decreases in the SNR.

The choice of whether phase dither is used in a system will

ultimately be decided by the system goals. If lower spurs are

desired at the expense of a slightly raised noise floor, it should

be employed. If a low noise floor is desired and the higher spurs

can be tolerated or filtered by subsequent stages, phase dither is

not needed.

Amplitude Dither

Amplitude dither can also be used to improve spurious perfor-

mance of the NCO. Amplitude dither is enabled by setting Bit 2.

Amplitude dither improves performance by randomizing the

amplitude quantization errors within the angular-to-Cartesian

conversion of the NCO. This option may reduce spurs at the

expense of a slightly raised noise floor. Amplitude dither and phase

dither can be used together, separately, or not at all.

Clear Phase Accumulator on Hop

When Bit 3 is set, the NCO phase accumulator is cleared prior

to a frequency hop. This ensures a consistent phase of the NCO

on each hop. The NCO phase offset is unaffected by this setting

and is still in effect. If phase-continuous hopping is desired, this

bit should be cleared and the last phase in the NCO phase regis-

ter will be the initiating point for the new frequency.

Input Enable Control

There are four different modes of operation for the input enable.

Each of the high speed input ports includes an IEN line. Any of

the four filter Channels 0 through 3 can be programmed to take

data from either of the two Input Ports A or B (see the WB

AD6635BB/PCB датащи(PDF) 26 Page - Analog Devices

AD6635BB/PCB датащи(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

датащи скачать

ссылки URL