AD6635BBSLASHPCB datasheet(43/60 Pages) AD

43 / 60 page

REV. 0

AD6635

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When these bits are 00 the input sample rate (fSAMP) of the

channel is equal to the rate of the high speed CLK signal. When

IEN is low, the data going into the channel is masked to 0. This

is an appropriate mode for TDD systems in which the receiver

may wish to mask off the transmitted data yet still remain in the

proper phase for the next receive burst.

When these bits are 01, the input sample rate is determined by

the fraction of the rising edges of CLK on which the IEN input

is high. For example, if IEN toggles on every rising edge of

CLK, then the IEN signal will only be sampled high on one out

of every two rising edges of CLK. This means that the input

sample rate fSAMP will be one-half the CLK rate.

When these bits are 10, the input sample rate is determined by

the rate at which the IEN pin toggles. The data that is captured

on the rising edge of CLK after IEN transitions from low to

high is processed. When these bits are 11, the accumulator and

sample CLK are determined by the rate at which the IEN pin

toggles. The data that is captured on the rising edge of CLK

after IEN transitions from high to low is processed. For

example, control modes 10 and 11 can be used to allow

interleaved data from either the A or B input ports and then

assigned to the respective channel. The IEN pin selects the data

Table XI. Channel Memory Map (Part 2)

Channel Address

Bit Width

Comments

rCIC2 Decimation – 1

MrCIC2 – 1

rCIC2 Interpolation – 1

LrCIC2 – 1

rCIC2 Scale

11: Exponent Invert

10: Exponent Weight

9–5: rCIC2_QUIET[4:0]

4–0: rCIC2_LOUD[4:0]

Reserved

Reserved (Must Be Written Low)

CIC5 Decimation – 1

MCIC5 – 1

CIC5 Scale

4–0: CIC5_SCALE[4:0]

Reserved

Reserved (Must Be Written Low)

97–9F

Unused

RCF Decimation – 1

MRCF – 1

RCF Decimation Phase

PRCF

RCF Number of Taps – 1

NTaps – 1

RCF Coefficient Offset

CORCF or RCFOFF

RCF Control Register

10: RCF Bypass BIST

9: RCF Input Select (Own 0, Other 1)

8: Program RAM Bank 1/0

7: Use Common Exponent

6: Force Output Scale

5–4: Output Format

1x: Floating Point 12 + 4

01: Floating Point 8 + 4

00: Fixed Point

3–0: Output Scale

such that one channel could be configured in Mode 10 and

another could be configured in Mode 11.

Bit 3 determines whether the phase accumulator of the NCO is

cleared when a hop occurs. The hop can originate from either

the Pin_SYNC or Soft_SYNC. When this bit is set to 0, the hop

is phase continuous and the accumulator is not cleared. When

this bit is set to 1, the accumulator is cleared to 0 before it

begins accumulating the new frequency word. This is appropriate

when multiple channels are hopping from different frequencies

to a common frequency.

Bits 2–1 control whether the dithers of the NCO are acti-

vated. The use of these features is heavily determined by the

system constraints. Consult the numerically controlled

oscillator (NCO) section for more detailed information on

the use of dither.

Bit 0 of this register allows the NCO frequency translation

stage to be bypassed. When this occurs, the data from the A

input port is passed down the I path of the channel and the

data from the B input port is passed down the Q path of the

channel. This allows a real filter to be performed on baseband

I and Q data. For Channels 4 to 7, C input port is I-path and

D input port is Q-path.

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