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AD6635

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INPUT DATA PORTS

The AD6635 features four high speed ADC Input Ports, A, B,

C, and D. The input ports allow for the most flexibility with a

single tuner chip. These can be diversity inputs or truly inde-

pendent inputs such as separate antenna segments. Channels 0

through 3 can take data from either of the input ports A or B

independently. Similarly, Channels 4 through 7 can take data

from either of the Input Ports C or D independently. For added

flexibility, each input port can be used to support multiplexed

inputs, such as found on the AD6600 or other ADCs with multi-

plexed outputs. This added flexibility allows up to eight different

analog sources to be processed simultaneously by the eight

internal AD6635 channels.

In addition, the front end of the AD6635 contains circuitry that

enables high speed signal level detection and control. This is

accomplished with a unique high speed level detection circuit

that offers minimal latency and maximum flexibility to control

up to four analog signal paths. The overall signal path latency

from input to output on the AD6635 can be expressed in high

speed clock cycles. The equation below can be used to calculate

the latency.

LATENCY

rCIC

CIC

TAPS

=+ +

726

()

MrCIC2 and MCIC5 are decimation values for the rCIC2 and CIC5

filters, respectively. NTAPS is the number of RCF taps chosen.

Input Data Format

Each input port consists of a 14-bit mantissa and 3-bit exponent. If

interfacing to a standard ADC, the exponent bits can be grounded.

If connected to a floating point ADC, such as the AD6600, the

exponent bits from that ADC product can be connected to the

input exponent bits of the AD6635. The mantissa data format is

twos complement, and the exponent is unsigned binary.

Input Timing

The data from each high speed input port is latched on the

rising edge of CLK. This clock signal is used to sample the

input port and clock the synchronous signal processing stages

that follow in the selected channels.

CLK

IN[13:0]

EXP[2:0]

DATA

tSI

tHI

Figure 24. Input Data Timing Requirements

The clock signals can operate up to 80 MHz and have a 50%

duty cycle. In applications using high speed ADCs, the ADC

sample clock or data valid strobe is typically used to clock the

AD6635.

tCLKL

tCLK

tCLKH

CLKn

Figure 25. CLKn Timing Requirements (n = 0, 1)

Input Enable Control

There are four Input Enable pins IENx (x = A, B, C, or D)

corresponding to individual Input Ports A through D. There are

four modes of operation possible while using each IEN pin.

Using these modes, it is possible to emulate operation of the

other RSPs such as the AD6620, which offer dual channel

modes normally associated with diversity operations. These

modes are IEN transition to Low, IEN transition to High, IEN

High, and Blank on IEN Low.

In the IEN High mode, the inputs and normal operations occur

when the Input Enable is High. In the IEN transition to Low

mode, normal operations occur on the first rising edge of the

clock after the IEN transitions to Low. Likewise in the IEN

transition to High mode, operations occur on the rising edge of

the clock after the IEN transitions to High. See the numerically

Controlled Oscillator section for more details on configuring the

Input Enable Modes. In Blank on IEN Low mode, the input

data is interpreted as zero when IEN is low.

A typical application for input modes would be to take the data

from an AD6600 Diversity ADC to one of the inputs of the

AD6635. The A/B_OUT from that chip would be tied to the

IEN of the corresponding input port. Then one channel within

the AD6635 would be set so that IEN transition to Low is

enabled. Another channel would be configured so that IEN

transition to High is enabled. This would allow two of the

AD6635 channels to be configured to emulate that AD6620 in

diversity mode and receive interleaved input data. Though the

NCO frequencies and other channel characteristics would need

to be set similarly, this feature allows the AD6635 to handle

interleaved data streams such as found on the AD6600.

The difference between the IEN transition to High and the

IEN High is found when a system clock is provided that is

higher than the data rate of the converter. It is often advanta-

geous to supply a clock that runs faster than the data rate so

that additional filter taps can be computed. This indeed leads

to better filtering. To ensure that other parts of the circuit

properly recognize the faster clock in the simplest manner,

the IEN transition to Low or High should be used. In this

mode, only the first clock edge that meets the setup and hold

times will be used to latch and process the input data. All other

clocks pulses are ignored by front end processing. However,

each clock cycle will still produce a new filter computation pair.

Gain Switching

The AD6635 includes circuitry that is useful in applications where

either large dynamic ranges exist, or where gain ranging converters

are employed. This circuitry allows digital thresholds to be set such

that an upper and a lower threshold can be programmed.

One such use of this may be to detect when an ADC is about to

reach full scale with a particular input condition. The results

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