AD6635BBSLASHPCB datasheet(40/60 Pages) AD

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AD6635

LINK PORT

The AD6635 has four configurable link ports that provide a

seamless data interface with the TigerSHARC DSP. Each link

port allows the AD6635 to write output data to the receive

DMA channel in the TigerSHARC for transfer to memory.

Since they operate independently of each other, each link port

can be connected to a different TigerSHARC or to different link

ports on the same TigerSHARC. Figure 39 shows how to con-

nect one of the four AD6635 link ports to one of the four

TigerSHARC link ports. Individual link ports are configured

through their respective registers.

AD6635

LCLKIN

LCLKOUT

LDAT

PCLK

TigerSHARC

LCLKIN

LCLKOUT

LDAT

PCLK

Figure 39. Link Port Connection between AD6635

and TigerSHARC

Link Port Data Format

Each link port can output data to the TigerSHARC in five

different formats: 2-channel, 4-channel, dedicated AGC,

redundant AGC with RSSI word, and redundant AGC without

RSSI word. Each format outputs 2 bytes of I data and 2 bytes of

Q data to form a 4-byte IQ pair. Since the TigerSHARC link

port transfers data in quad-word (16-byte) blocks, four IQ pairs

can make up one quad-word. If the channel data is selected (Bit

0 of 0x1B/0x1D = 0), then 4-byte IQ words of the four channels

can be output in succession, or alternating channel pair IQ

words can be output. Figures 40 and 41 show the quad-word

transmitted for each scenario with corresponding register values

for configuring each link port.

LINK PORT

A OR B

CH 0 I, Q

(4 BYTES)

CH 1 I, Q

(4 BYTES)

CH 2 I, Q

(4 BYTES)

CH 3 I, Q

(4 BYTES)

ADDR 0x1B OR 0x1D BIT 0 = 0, BIT 1 = 0

LINK PORT A

CH 0 I, Q

(4 BYTES)

CH 1 I, Q

(4 BYTES)

CH 0 I, Q

(4 BYTES)

CH 1 I, Q

(4 BYTES)

LINK PORT B

CH 2 I, Q

(4 BYTES)

CH 3 I, Q

(4 BYTES)

CH 2 I, Q

(4 BYTES)

CH 3 I, Q

(4 BYTES)

ADDR 0x1B OR 0x1D BIT 0 = 0, BIT 1 = 1

Figure 40. Link Port Data from RCF

If AGC output is selected (Bit 0 of 0x1B/0x1D = 1), then RSSI

information can be sent with the IQ pair from each AGC. Each

link port can be configured to output data from one AGC or

both link ports can output data from the same AGC. If both link

ports are transmitting the same data, then RSSI information

must be sent with the IQ words (Bit 2 = 0). Note that the actual

AGC RSSI is only 2 bytes (12 bits of RSSI word appended with

four zeros), so the link port sends 2 bytes of 0s immediately after

each RSSI word to make a full 16-byte quad-word.

LINK PORT

A OR B

AGC A I, Q

(4 BYTES)

AGC B I, Q

(4 BYTES)

AGC A I, Q

(4 BYTES)

AGC B I, Q

(4 BYTES)

ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 0, BIT 2 = 0

LINK PORT

A OR B

AGC A I, Q

(4 BYTES)

AGC A RSSI

(4 BYTES)

AGC B I, Q

(4 BYTES)

AGC B RSSI

(4 BYTES)

ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 0, BIT 2 = 1

LINK PORT A

AGC A I, Q

(4 BYTES)

AGC A RSSI

(4 BYTES)

AGC A I, Q

(4 BYTES)

AGC A RSSI

(4 BYTES)

AGC B I, Q

(4 BYTES)

AGC B RSSI

(4 BYTES)

AGC B I, Q

(4 BYTES)

AGC B RSSI

(4 BYTES)

LINK PORT B

ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 1, BIT 2 = 0

Figure 41. Link Port Data from AGC

Note that Bit 0 = 1, Bit 1 = 0, and Bit 2 = 1 is not a valid con-

figuration. Bit 2 must be set to 0 to output AGC A IQ and RSSI

words on link Port A, and AGC B IQ and RSSI words on link

Port B.

Link Port Timing

Link Ports A and B derive their clocks of PCLK0 and link Ports

C and D of PCLK1, which can be externally provided to the

chip (Addr 0x1E, Bit 0 = 0) or generated from the master clock

of the AD6635 (Addr 0x1E, Bit 0 = 1). This register boots to 0

(slave mode) and allows the user to control the data rate coming

from the AD6635. PCLK can be run as fast as 100 MHz.

The link port provides 1-byte data-words (Lx[7:0] pins) and

output clocks (LxCLKOUT pins) in response to a ready signal

(LxCLKIN pins) from the receiver, where x = A, B, C, or D.

Each link port transmits 8 bits on each edge of LCLKOUT,

requiring eight LCLKOUT cycles to complete transmission of

the full 16 bytes of a TigerSHARC quad-word.

D0 D1 D2 D3

D15

D0 D1 D2

NEXT QUAD-WORD

TigerSHARC READY TO

RECEIVE QUAD-WORD

WAIT > 6 CYCLES

TigerSHARC READY TO

RECEIVE NEXT QUAD-WORD

LCLKIN

LCLKOUT

LDAT[7:0]

Figure 42. Link Port Data Transfer

Due to the TigerSHARC link port protocol, the AD6635 must

wait at least six PCLK cycles after the TigerSHARC is ready to

receive data, as indicated by the TigerSHARC setting the respec-

tive AD6635 LCLKIN pin high. Once the AD6635 link port

has waited the appropriate number of PCLK cycles and has

begun transmitting data, the TigerSHARC does a connectivity

check by sending the AD6635 LCLKIN low and then high

while the data is being transmitted. This tells the AD6635 link

port that the TigerSHARC’s DMA is ready to receive the next

quad-word after completion of the current quad-word. Because

the connectivity check is done in parallel to the data transmis-

sion, the AD6635 is able to stream uninterrupted data to the

TigerSHARC.

The length of the wait before data transmission is a 4-bit pro-

grammable value in the link port control registers (0x1B and

0x1D, Bits 6–3). This value allows the AD6635 PCLK and the

TigerSHARC PCLK to be run at different rates and out of phase.

WAIT

ceil

LCLK

LCLK TSHARC

≥

ËÁ

¯˜

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