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AD6635BB/PCB датащи(PDF) 22 Page - Analog Devices |
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AD6635BB/PCB датащи(HTML) 22 Page - Analog Devices |
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22 / 60 page ![]() REV. 0 –22– AD6635 TIMING DIAGRAMS – MNM Microport Mode (MODE = 1) VALID ADDRESS VALID DATA CLK0 CLK1 DS (RD) RW ( WR) CS0 CS1 A[2:0] D[7:0] DTACK (RDY) NOTES 1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM FE OF DS TO THE FE OF DTACK. 2. tACC REQUIRES A MAXIMUM OF 9 CLK PERIODS. tSC tHC tHDS tHRW tHAM tACC tSAM tHAM tSAM tDDTACK Figure 22. MNM Microport Write Timing Requirements. CLK0 corresponds to CS0, and CLK1 to CS1. CS0 and CS1 both active (low) at the same time will cause errors in writing. CLK0 CLK1 DS (RD) RW ( WR) A[2:0] D[7:0] DTACK (RDY) tSC tACC tDDTACK NOTES 1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF DS TO THE FE OF DTACK. 2. tACC REQUIRES A MAXIMUM OF 13 CLK PERIODS. VALID ADDRESS VALID DATA tSAM tHC tHDS tHAM CS0 CS1 Figure 23. MNM Microport Read Timing Requirements. CLK0 corresponds to CS0, and CLK1 to CS1. CS0 and CS1 both active (low) at the same time will cause contention on data bus. |
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