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AD6635BB/PCB датащи(PDF) 41 Page - Analog Devices

номер детали AD6635BB/PCB
подробное описание детали  4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)
PDF  60 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD6635BB/PCB датащи(HTML) 41 Page - Analog Devices

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REV. 0
AD6635
–41–
WAIT ensures that the amount of time the AD6635 needs to
wait to begin data transmission is at least equal to the minimum
amount of time the TigerSHARC is expecting it to wait. If the
PCLK of the AD6635 is out of phase with the PCLK of the
TigerSHARC and the argument to the ceil( ) function is an
integer, then WAIT must be strictly greater than the value given
in the above formula. If the LCLKs are in phase, the maximum
output data rate is
ff
LCLK
LCLK
TSHARC
__
34
15
6
£¥
otherwise, it is
ff
LCLK
LCLK
TSHARC
__
34
14
6
£¥
TigerSHARC Configuration
Since the AD6635 is always the transmitter in this link and the
TigerSHARC is always the receiver, the following values can be
programmed into the LCTL register for the link port used to
receive AD6635 output data. “User” means that the actual
register value depends on the user’s application.
Table IX. TigerSHARC LCTLx Register Configuration
VERE
0
SPD
User
LTEN
0
PSIZE
1
TTOE
0
CERE
0
LREN
1
RTOE
1
Table X. Channel Memory Map (Part 1)
Channel Address
Register
Bit Width
Comments
00–7F
Coefficient Memory (CMEM)
20
128
20-Bit Memory
80
CHANNEL SLEEP
1
0: SLEEP Bit from EXT_ADDRESS 3
81
Soft_Sync Control Register
2
1: Hop
0: Start
82
Pin_SYNC Control Register
3
2: First SYNC Only
1: Hop_En
0: Start_En
83
Start Holdoff Counter
16
Start Holdoff Value
84
NCO Frequency Holdoff Counter
16
NCO_FREQ Holdoff Value
85
NCO Frequency Register 0
16
NCO_FREQ[15:0]
86
NCO Frequency Register 1
16
NCO_FREQ[31:16]
87
NCO Phase Offset Register
16
NCO_PHASE[15:0]
88
NCO Control Register
9
8–7: SYNC Input Select[1:0]
6: WB Input Select B/A
5–4: Input Enable Control
11: Clock on IEN Transition to Low
10: Clock on IEN Transition to High
01: Clock on IEN High
00: Mask on IEN Low
3: Clear Phase Accumulator on HOP
2: Amplitude Dither
1: Phase Dither
0: Bypass (A Input
Æ I-Path, B Æ Q)
89–8F
Unused
(C Input
ÆI-Path, D ÆQ)
MEMORY MAP
This section describes the memory maps for channel, memory,
and for the input and output control registers.



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