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AD6635BB/PCB датащи(PDF) 49 Page - Analog Devices |
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AD6635BB/PCB датащи(HTML) 49 Page - Analog Devices |
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49 / 60 page ![]() REV. 0 AD6635 –49– Table XV. Memory Map for Output Port Control Registers (continued) Channel Address (hex) Register Bit Width Comments 3: Channel 2 2: Channel 1/AGC B Enable 1: Channel 0/AGC A Enable 0: AGC_CH Select 1: Data Comes from AGCs 0: Data Comes from Channels 1B Link A Control 8 7: Link Port A Enable 6–3: Wait 2: No RSSI Word 1: Don’t Output RSSI Word 0: Output RSSI Word 1: Channel Data Interleaved 1: 2-Channel Mode/Separate A, B 0: 4-Channel Mode/A, B Same Port 0: AGC_CH Select 1: Data Comes from AGCs 0: Data Comes from Channels 1C Parallel B Control 8 7–6: Reserved 5: Parallel Port Data Format 1: 8-Bit Parallel I, Q 0: 16-Bit Interleaved I, Q 4: Channel 3 3: Channel 2 2: Channel 1/AGC B Enable 1: Channel 0/AGC A Enable 0: AGC_CH Select 1: Data Comes from AGCs 0: Data Comes from Channels 1D Link B Control 8 7: Link Port A Enable 6–3: Wait 2: No RSSI Word 1: Don’t Output RSSI Word 0: Output RSSI Word 1: Channel Data Interleaved 1: 2-Channel Mode/Separate A, B 0: 4-Channel Mode/A, B Same Port 0: AGC_CH Select 1: Data Comes from AGCs 0: Data Comes from Channels 1E Port Clock Control 3 2–1: PCLK Divisor 0: PCLK Master/Slave1 0: Slave 1: Master 1PCLK boots as slave to avoid contention. |
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