AD6635BBSLASHPCB datasheet(35/60 Pages) AD

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AD6635

–35–

Figure 32 (Block Diagram of the AGC), and the operation is

similar to the Desired Signal Level mode.

First, the data from the gain multiplier is truncated to a lower

resolution (4, 5, 6, 7, 8, 10, 12, or 16 bits) as set by the AGC

control word. An error term (both I and Q) is generated that is

the difference between the signals before and after truncation.

This term is passed to the complex squared magnitude block for

averaging and decimating the update samples and taking their

square root to find rms samples, just as in Desired Signal

Level mode. In place of the request desired signal level, a

desired clipping level is subtracted, leaving an error term to be

processed by the second-order loop filter. The rest of the loop

operates the same way as the Desired Signal Level mode. This

way the truncation error is calculated and the AGC loop oper-

ates to maintain a constant truncation error level.

Apart from Bit 4 of the AGC control words, the only other

mode, is that the Desired Clipping level is stored in the AGC

Desired Level registers (0x0C, 0x15) instead of the Request

Signal Level (as in Desired Signal Level mode).

Synchronization

In scenarios where AGC output is connected to a RAKE receiver,

the RAKE receiver can synchronize the average and update sec-

tion to update the average power for AGC error calculation and

loop filtering. This external sync signal synchronizes the AGC

changes to the RAKE receiver and makes sure that the AGC

gain does not change over a symbol period, resulting in more

accurate estimation. Such synchronization can be accomplished

by setting the appropriate bits of the AGC control register.

When the channel comes out of sleep, it loads the AGC holdoff

counter value and starts counting down, clocked by the Master

clock. When this counter reaches zero, the CIC filter of the

AGC starts decimation and updates the AGC loop filter based

on the set CIC decimation value.

Further, whenever the user wants to synchronize the start of

decimation for a new update sample, an appropriate holdoff

value can be set in the AGC Holdoff counter (0x0B, 0x13) and

then the Sync now bit (Bit 3) in the AGC control word is set.

Upon setting this bit, the holdoff counter value is counted down

and a CIC decimated value is updated on the count of zero.

Along with updating a new value, the CIC filter accumulator

can be reset if Init on Sync bit (Bit 2) of the AGC control word

is set. Each sync will initiate a new sync signal unless first sync

only bit (Bit 1) of the AGC control word is set. If this bit is not

set, again the holdoff counter is loaded with the value in the

Holdoff register to count down and repeat the same process.

These additional features make the AGC synchronization more

flexible and applicable to varied circumstances.

Addresses 0x0A–0x11 have been reserved for configuring AGC

A, and addresses 0x12–0x19 have been reserved for configuring

AGC B. The register specifications are detailed in the Memory

Map for Output Port Control Registers section.

USER-CONFIGURABLE BUILT-IN SELF TEST (BIST)

The AD6635 includes two built-in test features to test the integ-

rity of each channel. The first is a RAM BIST and is intended

to test the integrity of the high speed random access memory

within the AD6635. The second is Channel BIST, which is

designed to test the integrity of the main signal paths of the

AD6635. Each BIST function is independent of the other,

meaning that each channel can be tested independently at the

same time.

RAM BIST

The RAM BIST can be used to validate functionality of the

on-chip RAM. This feature provides a simple pass/fail test,

which will give confidence that the channel RAM is operational.

The following steps should be followed to perform this test.

1. The channels to be tested should be put into Sleep mode via

the external address register 0x011.

2. The RAM BIST Enable bit in the RCF register 0xA8

should be set high.

3. Wait 1600 clock cycles.

4. Register 0xA8 should be read back. If Bit 0 is high, the test

is not yet complete. If Bit 0 is low, the test is complete and

Bits 1 and 2 indicate the condition of the internal ram. If

Bit 1 is high, then CMEM is bad. If Bit 2 is high, then

DMEM is bad.

Table VIII. BIST Register 0xA8

0xA8

Coefficient MEM

Data MEM

XX1

Test incomplete

000

PASS

010

FAIL

PASS

100

PASS

FAIL

110

FAIL

Channel BIST

The Channel BIST is a thorough test of the selected AD6635

signal path. With this test mode, it is possible to use externally

supplied vectors or an internal pseudorandom generator. An

error signature register in the RCF monitors the output data of

the channel, and is used to determine whether the proper data

exits the RCF. If errors are detected, each internal block may be

bypassed and another test can be run to debug the fault. The I

and Q paths are tested independently. The following steps

should be followed to perform this test.

1. The channels to be tested should be configured as required

for the application, setting the decimation rates, scalars,

and RCF coefficients.

2. The channels should remain in the Sleep mode.

3. The Start Holdoff counter of the channels to be tested

should be set to 1.

4. Memory locations 0xA5 and 0xA6 should be set to 0.

5. The Channel BIST located at 0xA7 should be enabled by

setting Bits 19–0 to the number of RCF outputs to observe.

6. Bit 4 of External Address Register 5 should be set high to

start the soft sync.

7. Set the SYNC bits high for the channels to be tested.

8. Bit 6 must be set to 0 to allow the user to provide test

vectors. The internal pseudorandom number generator

may also be used to generate an input sequence by setting

Bit 7 high.

9. An internal full-scale sine wave can be inserted when Bit 6

is set to 1 and Bit 7 is cleared.

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