AD6635BBSLASHPCB datasheet(53/60 Pages) AD

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AD6635

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0x1D Link Port Control B

Data is output through either a parallel port interface or a link

port interface. The link port provides an efficient data link

between the AD6635 and a TigerSHARC DSP, and can be

enabled by setting Bit 7 = 1.

Bit 0 selects which data is output on Link Port B. When Bit 0 = 0,

Link Port B outputs data from the RCF according to the format

specified by Bit 1. When Bit 0 = 1, Link Port B outputs the data

from the AGCs according to the format specified by Bits 1 and 2.

Bit 1 has two different meanings that depend on whether data is

coming from the AGCs or from the RCFs. When data is coming

from the RCFs (Bit 0 = 0), Bit 1 selects between 2- and

4-channel data mode. Bit 1 = 1 indicates Link Port A transmits

RCF IQ words alternately from Channels 0 and 1. When Bit 1 = 1,

Link Port B outputs RCF IQ words from each of the four chan-

nels in succession: 0, 1, 2, then 3. However, when AGC data is

selected (Bit 0 = 1), Bit 1 selects the AGC data output mode. In

this mode, when Bit 1 = 1, Link Port B outputs AGC B IQ and

RSSI words. In this mode, RSSI words must be included by

setting Bit 2 = 0. However, if Bit 0 = Bit 1 = 0, AGC A and

B are alternately output on Link Port B, and the inclusion or

exclusion of the RSSI words is determined by Bit 2.

Bit 2 selects if RSSI words are included or not in the data out-

put. If Bit 1 = 1, Bit 2 = 0. Since the RSSI words are only 2

bytes long (12 bits appended with 4 zeros) and the IQ words are

4 bytes long, the RSSI words are padded with zeros to give a full

16-byte TigerSHARC quad-word. If AGC output is not selected

(Bit 0 = 0), this bit can be any value.

Bits 6–3 specify the programmable delay value for Link Port B

between the time the link port receives a data ready from the

receiver and the time it transmits the first data-word. The link

port must wait at least six cycles of the receiver’s clock, so this

value allows the user to use clocks of differing frequency and

phase for the AD6635 link port and the TigerSHARC link port.

There is more information on the limitations and relationship of

these clocks in Link Ports section.

0x1E Port Clock Control

Bit 0 determines whether PCLKn is supplied externally by the

user or derived internally in the AD6635. If PCLKn is derived

internally from CLK (Bit 0 = 1), it is output through the PCLKn

pin as a master clock. PCLK0 is derived from CLK0, and

PCLK1 from CLK1. For other applications, PCLK will be pro-

vided by the user as an input to the AD6635 via the PCLK pin.

Bits 2 and 1 allow the user to divide CLK by an integer value to

generate PCLKn. The integer divisors for bit settings are 00 =

1, 01 = 2, 10 = 4, 11 = 8, respectively.

MICROPORT CONTROL

The AD6635 has an 8-bit microprocessor port and two serial

control ports. The use of each of these ports is described sepa-

rately below. The interaction of the ports is then described. The

microport interface is a multimode interface that is designed to

give flexibility when dealing with the host processor. There are

two modes of bus operation: Intel nonmultiplexed mode

(INM), and Motorola nonmultiplexed mode (MNM). The

mode is selected based on the host processor and which mode is

best suited to that processor. The microport has an 8-bit data

bus (D[7:0]), 3-bit address bus (A[2:0]), four control pin lines

(

CS0, CS1, DS or RD, and RW or WR), and one status pin

(

DTACK or RDY). The functionality of the control signals and

status line changes slightly depending upon the mode that is

chosen (INM or MNM). Refer to the timing diagrams at the

beginning of the data sheet and the following descriptions for

details on the operation of both modes.

External Memory Map

The external memory map is used to gain access to the channel

address space and input/output address space described previ-

ously. The 8-bit data and address buses are used to access this

set of eight registers that can be seen in Table XVI. These registers

are collectively referred to as the external interface registers

since they control all accesses to the channel address space as

well as input/output chip functions. The use of each of these

individual registers is described below in detail. It should be

noted that the serial control interface has the same memory map

as the microport interface and can carry out the exact same

functions, although at a slower rate.

The external address space defined by the eight registers can

be treated as two address spaces with each address space

having its own chip select pins (

CS0 and CS1). For pro-

gramming through microport Channels 0–3, Input Ports A

and B, Half-band filters and AGCs A and B, and Output Ports

A and B,

CS0 should be used. For programming through

microport Channels 4–7, Input Ports C and D, Half-band

filters and AGCs C and D, and Output Ports C and D,

CS1

should be used.

Though only external address map corresponding to

CS0 is

explained in this data sheet, in all places it should also be

replaced by

CS1 to complete the functionality description.

When this is done, Channels 0–3 should be replaced by Chan-

nels 4–7, Input/Output Ports A and B should be replaced by

Input/Output Ports C and D, respectively, and Half-band/

AGCs A and B should be replaced by Half-band/AGCs C and

D, respectively.

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