AD6635BBSLASHPCB datasheet(47/60 Pages) AD

47 / 60 page

REV. 0

AD6635

–47–

is prior to the ADC, there is a latency associated with the ADC

and with the settling of the gain change. This register allows the

internal delay of the LIA-A and LIA-B signal to be programmed.

0x04 Lower Threshold B

This word is 10 bits wide and maps to the 10 MSBs of the

mantissa. If the upper 10 bits of Input Port B are less than or

equal to this value, the lower threshold has been met. In nor-

mal chip operation, this starts the dwell time counter. If the

input signal increases above this value, the counter is reloaded

and waits for the input to drop back to this level.

0x05 Upper Threshold B

This word is 10 bits wide and maps to the 10 MSBs of the

mantissa. If the upper 10 bits of Input Port B are greater than

or equal to this value, the upper threshold has been met. In

normal chip operation, this will cause the appropriate LI pin

(LIB-A or LIB-B) to become active.

0x06 Dwell Time B

This sets the time that the input signal must be at or below the

lower threshold before the LI pin is deactivated. For the input

level detector to work, the dwell time must be set to at least 1. If

set to 0, the LI functions are disabled.

This is a 20-bit register. When the lower threshold is met fol-

lowing an excursion into the upper threshold, the dwell time

counter is loaded and begins to count high speed clock cycles as

long as the input is at or below the lower threshold. If the signal

increases above the lower threshold, the counter is reloaded and

waits for the signal to fall below the lower threshold again.

0x07 Gain Range B Control Register

Bit 4 determines the polarity of LIB-A and LIB-B. If this bit

is clear, the LI signal is high when the upper threshold has

been exceeded. However, if this bit is set, the LI pin is low

when active. This allows maximum flexibility when using

this function.

Bit 3 determines if the input consists of a single channel or

TDM channels, such as when using the AD6600. If this bit is

cleared, a single ADC is assumed. In this mode, LIB-A func-

tions as the active output indicator. LIB-B provides the

compliment of LIB-A. However, if this bit is set, the input is

determined to be dual-channel and determined by the state of

the IENB pin. If the IENB pin is low, the input detection is

directed to LIB-A. If the IENB pin is high, the input is directed

to LIB-B. In either case, Bit 4 determines the actual polarity of

these signals.

Bits 2–0 determine the internal latency of the gain detect func-

tion. When the LIB-A and LIB-B pins are made active, they are

typically used to change an attenuator or gain stage. Since this is

prior to the ADC, there is a latency associated with the ADC and

with the settling of the gain change. This register allows the inter-

nal delay of the LIB-A and LIB-B signal to be programmed.

Table XV. Memory Map for Output Port Control Registers

Channel Address (hex)

Bit Width

Comments

Port A Control Register

3: Port A Enable

2–1: HB A Signal Interleaving

All 4 Channels

Channels 0, 1, 2

Channels 0, 1

Channel 0

0: Bypass

Port B Control Register

2: Port B Enable

1: HB A Signal Interleaving

1Channels 2, 3

0Channel 2

0: Bypass

AGC A Control Register

7–5: Output Word Length

111

4 bits

110

5 bits

101

6 bits

100

7 bits

011

8 bits

010

10 bits

001

12 bits

000

16 bits

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