AD6635BBSLASHPCB datasheet(30/60 Pages) AD

30 / 60 page

REV. 0

–30–

AD6635

Table IV. SSB CIC5 Alias Rejection Table (fSAMP2 = 1).

Bandwidths are given as percentage of fSAMP2.

MCIC5

–50 dB –60 dB –70 dB –80 dB

–90 dB –100 dB

10.227 8.078

6.393

5.066

4.008

3.183

7.924

6.367

5.110

4.107

3.297

2.642

6.213

5.022

4.057

3.271

2.636

2.121

5.068

4.107

3.326

2.687

2.170

1.748

4.267

3.463

2.808

2.270

1.836

1.480

3.680

2.989

2.425

1.962

1.588

1.281

3.233

2.627

2.133

1.726

1.397

1.128

2.881

2.342

1.902

1.540

1.247

1.007

2.598

2.113

1.716

1.390

1.125

0.909

2.365

1.924

1.563

1.266

1.025

0.828

2.170

1.765

1.435

1.162

0.941

0.760

2.005

1.631

1.326

1.074

0.870

0.703

1.863

1.516

1.232

0.998

0.809

0.653

1.740

1.416

1.151

0.932

0.755

0.610

1.632

1.328

1.079

0.874

0.708

0.572

1.536

1.250

1.016

0.823

0.667

0.539

1.451

1.181

0.960

0.778

0.630

0.509

1.375

1.119

0.910

0.737

0.597

0.483

1.307

1.064

0.865

0.701

0.568

0.459

1.245

1.013

0.824

0.667

0.541

0.437

1.188

0.967

0.786

0.637

0.516

0.417

1.137

0.925

0.752

0.610

0.494

0.399

1.090

0.887

0.721

0.584

0.474

0.383

1.046

0.852

0.692

0.561

0.455

0.367

1.006

0.819

0.666

0.540

0.437

0.353

0.969

0.789

0.641

0.520

0.421

0.340

0.934

0.761

0.618

0.501

0.406

0.328

0.902

0.734

0.597

0.484

0.392

0.317

0.872

0.710

0.577

0.468

0.379

0.306

0.844

0.687

0.559

0.453

0.367

0.297

0.818

0.666

0.541

0.439

0.355

0.287

RAM COEFFICIENT FILTER

The final signal processing stage for each individual channel is a

sum-of-products decimating filter with programmable coeffi-

cients. A simplified block diagram is shown below. The data

memories I-RAM and Q-RAM store the 160 most recent com-

plex samples from the previous filter stage with 20-bit resolution.

The coefficient memory, CMEM, stores up to 256 coefficients

with 20-bit resolution. On every CLK cycle, one tap for I and

one tap for Q are calculated using the same coefficients. The

RCF output consists of 24-bit data.

160

20B

I-RAM

IIN

IOUT

256

20B

C-RAM

160

20B

Q-RAM

QIN

QOUT

Figure 30. RAM Coefficient Filter (RCF) Block Diagram

RCF Decimation Register

Each RCF channel can be used to decimate the data rate. The

decimation register is an 8-bit register and can decimate from

1 to 256. The RCF decimation is stored in 0xA0 in the form of

MRCF – 1. The input rate to the RCF is fSAMP5.

RCF Decimation Phase

The RCF decimation phase can be used to synchronize multiple

filters within a chip. This is useful when using multiple channels

within the AD6635 to implement a polyphase filter allowing the

resources of several RCF filters to be paralleled. In such an

application, two RCF filters would be processing the same data

from the CIC5. However, each filter will be delayed by one half

the decimation rate, thus creating a 180

∞ phase difference between

the two halves.

The AD6635 filter channel uses the value stored in this register

to preload the RCF counter. Therefore, instead of starting from

0 (coefficient number 0), the counter is loaded with

Counter

decimation phase

Number of channels used

RCF decimationin each channel

CLK

RCF

¥¥

thus creating an offset in the processing that should be equiva-

lent to the required processing delay. The number of channels

or RCFs used to process one carrier is used in the above equa-

tion. fCLK is the input clock rate to the AD6635 and fRCF is the

input sample rate to the RCF from the CIC5 stage. This data is

stored in 0xA1 as an 8-bit number. The RCF decimation phase

can be used only when the ratio of RCF decimation and num-

ber of RCFs used is an integer.

RCF Filter Length

The maximum number of taps this filter can calculate, NTAPS, is

given by the equation below. The value NTAPS – 1 is written to

the Channel register within the AD6635 at address 0xA2.

TAPS

CLK

RCF

SAMP

ËÁ

¯˜

min

160

The function “min” used above gives the minimum of all the

expressions inside the parenthesis.

The RCF coefficients are located in addresses 0x00 to 0x7F and

are interpreted as 20-bit twos complement numbers. When

writing the coefficient RAM, the lower addresses will be multi-

plied by relatively older data from the CIC5 and the higher

coefficient addresses will be multiplied by relatively newer data

from the CIC5. The coefficients need not be symmetric and the

coefficient length, NTAPS, may be even or odd. If the coefficients

are symmetric, then both sides of the impulse response must be

written into the coefficient RAM.

Although the base memory for coefficients is only 128 words

long, the actual length is 256 words long. There are two pages,

each 128 words long. The page is selected by Bit 8 of 0xA4.

AD6635BB/PCB датащи(PDF) 30 Page - Analog Devices

AD6635BB/PCB датащи(HTML) 30 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

датащи скачать

ссылки URL