AD6635BBSLASHPCB datasheet(5/60 Pages) AD

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AD6635

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ARCHITECTURE

Each channel of the AD6635 has four signal processing stages:

a Frequency Translator, a second-order Resampling Cascaded

Integrator Comb FIR Filter (rCIC2), a fifth-order Cascaded

Integrator Comb FIR Filter (CIC5), and a RAM Coefficient

FIR Filter (RCF). Multiple modes are supported for clocking

data into and out of the chip, and for providing flexibility for inter-

facing to a wide variety of digitizers. Programming and control is

accomplished via serial and/or microprocessor interfaces.

Frequency translation is accomplished with a 32-bit complex

Numerically Controlled Oscillator (NCO). Real data entering

this stage is separated into inphase (I) and quadrature (Q) com-

ponents by multiplying with the complex NCO word. This stage

translates the input signal from a digital intermediate frequency

(IF) to digital baseband. Phase and amplitude dither may be

enabled on-chip to improve spurious performance of the NCO.

A phase-offset word is available to create a known phase rela-

tionship between multiple AD6635s or between channels.

Following frequency translation is a fixed coefficient, high speed,

second-order, Resampling Cascade Integrator Comb (rCIC2) filter

that reduces the sample rate based on the ratio between the deci-

mation and interpolation registers.

The next stage is a fifth-order Cascaded Integrator Comb (CIC5)

filter whose response is defined by the decimation rate. The pur-

pose of these filters is to reduce the data rate to the final filter stage

(RCF), so that it can calculate more taps for the same RCF band-

width. The CIC5 filter has better antialiasing (filtering) compared

to rCIC2. In light of this, the user is advised to use this filter only if

resampling is required or if the required decimation cannot be

handled by CIC5 alone.

The final stage is a sum-of-products FIR filter with program-

mable 20-bit coefficients, and decimation rates programmable

from 1 to 256 (1 to 32 in practice). The RAM Coefficient FIR

Filter (RCF) can handle a maximum of 160 taps.

The data coming out of the RCF can be sent to output ports or

to an interleaver. This section can interleave data from more

than one channel. One carrier can be processed using more than

one channel and the interleaver will interleave the data back into

the output section. This way, processing power from more than

one channel can be used for one carrier.

The interleaved data is sent into a fixed coefficient half-band

interpolation filter where data is interpolated by a factor of two.

Digital AGC following the half-band filter has a gain range of

96.3 dB. This AGC section is completely programmable in

terms of its response. Four each of half-band filters and AGCs

are present in the AD6635, as shown in the Functional Block

Diagram. These half-band filters and AGC sections can be

bypassed independent of each other.

The overall filter response for the AD6635 is the composite of

all decimating and interpolating stages. Each successive filter

stage is capable of narrower transition bandwidths, but requires

a greater number of CLK cycles to calculate the output. More

decimation in the first filter stage will minimize overall power

consumption. Each independent filter stage can be bypassed in

a unique way. Data from the chip is interfaced to the DSP via

either a high speed parallel port or a TigerSHARC compatible

link port. Each output can be independently configured to use

either the parallel port or the link port.

Figure 1 illustrates the tuning function of the AD6635 NCOs to

select and filter a single channel from a wide input spectrum.

The frequency translator “tunes” the desired carrier to base-

band. Figure 2 shows the combined filter response of the rCIC2,

CIC5, and RCF filters for a sample filter configuration.

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