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10.0 Legacy Functional Blocks (Continued)

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Revision1.2

10.2 PARALLEL PORT

10.2.1

General Description

The Parallel Port supports all IEEE1284 standard communication modes:

Compatibility (known also as Standard or SPP).

Bidirectional (known also as PS/2).

FIFO.

EPP (known also as Mode 4).

ECP (with an optional Extended ECP mode).

10.2.2

Parallel Port Register Map

The Parallel Port includes two groups of runtime registers, as follows:

• A group of 21 registers at first level offset, sharing 14 entries. Three of these registers (at offsets 403h, 404h and 405h)

are used only in the Extended ECP mode.

• A group of four registers, used only in the Extended ECP mode, accessed by a second level offset.

EPP and second level offset registers are available only when the base address is 8-byte aligned.

The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime reg-

isters are used and which address bits are used for the base address. See Tables 60 and 61 for a listing of all registers, their

offset addresses and the associated modes. All registers are VDD powered.

Table 60. Parallel Port Registers at First Level Offset

Offset

Mnemonic

Mode(s)

Type

00h

DATAR

0,1

Data

R/W

AFIFO

ECP FIFO (Address)

DTR

Data (for EPP)

R/W

01h

DSR

0,1,2,3

Status

STR

Status (for EPP)

02h

DCR

0,1,2,3

Control

R/W

CTR

Control (for EPP)

R/W

03h

ADDR

EPP Address

R/W

04h

DATA0

EPP Data Port 0

R/W

05h

DATA1

EPP Data Port 1

R/W

06h

DATA2

EPP Data Port 2

R/W

07h

DATA3

EPP Data Port 3

R/W

400h

CFIFO

DFIFO

TFIFO

CNFGA

PP Data FIFO

ECP Data FIFO

Test FIFO

Conﬁguration A

R/W

401h

CNFGB

Conﬁguration B

402h

ECR

0,1,2,3

Extended Control

R/W

403h

EIR1

1. These registers are extended to the standard IEEE1284 registers. They

are only accessible when enabled by bit 4 of the Parallel Port Conﬁguration

0,1,2,3

Extended Index

R/W

404h

EDR1

0,1,2,3

Extended Data

R/W

405h

EAR1

0,1,2,3

Extended Auxiliary Status

R/W

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