ACE9050

5

Internal

Description

Keypad scan input/input port

Keypad scan input/input port

Keypad scan input/input port

Keypad scan input/input port

External Interrupt (also Bit1 Input Port1)

External Interrupt (also Bit0 Input Port1)

SynthBus Data Line

SynthBus 126kHz Clock

1 = Service Mode

Latch, programmable length. (To ACE9030, LATCHC pin)

Output Port2 Bit 6: High Current Driver

IF Counter Output for Emulation

(input in Test mode)

Latch O/P (To ACE9030 receiver Interface, LATCHB pin)

Output Port2 Bit 7: High Current Driver

Latch O/P (To ACE9040, LEN )

Output Port2 Bit 2/Pulse Width Modulator #2 Output/

SynthBus Latch O/P.

Bidirectional serial inter-chip data, to/from the ACE9030

1 = CPU Emulation Mode

CPU Interrupt for Emulation

(input in Test mode)

Power On/Off

Ground

Ground

Digital Supply

External reset output

1·008MHz Clock for ACEBus, ACE9030 and ACE9040

0 = Chip reset

Address input for Emulation only

Address input for Emulation only

8.064MHz clock/Out Port 2 bit 0

Read/Write

(Input during Emulation)

Beep, Alarm, Ring Tone Output

CPU Port 2 bit 3 or Serial interface (SCI) input

Output Port 2 Bit 1/Pulse Width Modulator #1 Output

Processor Clock

(Input during Emulation)

Carrier detect from RX

PD

PD

PD

PD

PD

PD

-

-

None

-

-

PU

-

-

-

-

None

PD

-

-

-

-

-

-

-

None

PU

PU

-

None

-

None

-

None

None

KPI [3]

KPI [2]

KPI [1]

KPI [0]

INRQ1

INRQ0

SYNTHDATA

SYNTHCLK

SERV

LATCH3

OUTP2 [6]

ICN

LATCH1

OUTP2[7]

LATCH0

OUTP2[2]/PWM2/

LATCH2

DTFG

EMUL

IRQN

POFFN

EXRESN

C1008

MRN

A15

A14

CPUCL/OUTP2 [0]

R/W

BAR

DTMS

OUTP2 [1]/PWM 1

ECLK

RXCD

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

EPORT

EPORT

EPORT

EPORT

EPORT

EPORT

SINT

SINT

WDATO

SINT

EPORT

IFC

SINT

EPORT

SINT

PWM

SINT

BINT/CPU

CPU

WDATO

WDATO

CLK

WDATO

BINT

BINT

CLK/EPORT

BINT

BAR

CPU

PWM

CLK

WDATO

Block

Type

I

I

I

I

I

I

O

O

I

O

O

O

(I)

O

O

O

O

I/O

I

O

(I)

O

O

O

I

I

I

O

O

(I)

O

I/O

O

O

(I)

I

Table 1 (continued)

Pin

Name

ABBREVIATIONS

BAR

Beep, Alarm and Ring tone generator

BAUD

Baud Rate generator

BINT

Bus Interface

MEMB

Memory Bank switching

CLK

Clock generator

CPU

6303 microprocessor unit

DEC

Decoder

EPORT

External Port

IFC

IF Control counter

MODEM

AMPS/TACS Modem

PWM

Pulse Width Modulator and MUX

SINT

Serial Inter-chip interface

WDATO

Watchdog/Autonomous Time Out

PU

Internal Pullup resistor present

PD

Internal Pulldown resistor present

Table 2

UNUSED INPUTS

Input or bidirectional pins must have a suitable pullup or pulldown reststor if they are configured as inputs, with no external drive. Some

inputs have an internal pullup or pulldown resistor of the order of 100k

Ω; this value is suitable if the pin is not subject to excessive noise

or residual current greater than 15

µA. If the pins shown in Table 2 are not used in the system, an external resistor will be required.

Pin

Name

4

7

8

9

12

13

14

DFMS

P1 [7]

P1 [6]

P1 [5]

P1 [4]

P1 [3]

P1 [2]

Pin

Name

15

16

51

52

53

54

60

P1 [1]

P1 [0]

RXSAT

INP1 [2]

INP1 [3]

INP1 [4]

AFC_IN/RXDATA

Pin

Name

61

74

82

91

97

100

TXPOW

SERV

DTFG (Requires

programming resistor)

MRN

DTMS

RXCD

NOTE: P1 [7:0], DFMS and DTMS are configured as inputs upon reset.