ACE9050 datasheet(25/52 Pages) MITEL

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ACE9050

caused by the software code entering an illegal state. This could

be due to an incorrect sequence being entered by the user or a

glitch on either the data or address bus causing the wrong

instruction to be executed.

The Watchdog is a 4-second counter which is always counting

and when it overflows a system reset is generated. This will reset

the ACE9050 and drive the external reset low for 100ms. It will

not reset POFFN, so the phone will not turn off. Refer to the

‘Autonomous Time Out (ATO)’ section for more details. To

prevent the system reset the Watchdog counter must be cleared.

This will prevent the system reset for 4 seconds. The following

actions clear the Watchdog counter:

1. In service mode the counter is permanently cleared, preventing

the system reset.

2. MRN low clears the Watchdog counter. The counter thus

starts when MRN goes high.

3. The processor making a write access to the Watchdog

Thus in normal operation the software code must be sure to

access the Watchdog register once every 4 seconds to prevent

a reset.

External Pins

MRN Master Reset (pin 91)

ThisactivelowinputcompletelyresetstheACE9050Inte~rated

circuit. It prevents the Watchdog timer from counting. The

ACE9050 will be reset for the duration of the MRN pulse plus an

additional 100ms. The clock must be running for the device to

reset correctly.

EXRESN External Reset (pin 89)

This active low output is provided for an external reset

function. It is active for a minimum of 100ms in the case of a

Watchdog reset. In the case of a MRN reset EXRESN will be low

for the duration of MRN being low plus an additional 100ms, as

shown in Fig. 18.

devices in an I2C system is very simple because they connect

directly to the two bus lines: a serial data line (SDA) and a serial

clock line (SCL). A prototype system or final product version can

easily be modified by ‘clippinq’ or ‘unclipping’ ICs to or from the

bus. The I2C is a reliable, multi-Master bus with integrated

addressing and data transfer protocols. The multi-Master

capability of the I2C is very important, although many designs do

not require it.

Both lines of the I2C bus are connected to a positive supply

via a pull-up resistor, and remain high when the bus is not

busy. Each device is recognised by a unique address, and

can operate as either a transmitter or a receiver, depending

upon the function of the device.

When a data transfer takes place on the bus, a device can

either be a Master or a Slave. The device which initiates the

transfer, and generates the clock signals for this transfer, is

the Master. At that time, any device addressed is considered

to be a Slave. It is important to note that a Master could either

be a transmitter or a receiver; a Master microcontroller may

send data to an EEPROM acting as a transmitter, and then

interrogate the EEPROM for its contents acting as a receiver,

in both cases performing as the Master initiating the transfer.

In the same manner, a Slave could be both a receiver and a

transmitter.

One data bit is transferred during each clock pulse. The

data on the SDA line must remain stable during the high

period of the clock pulse in order to be valid. Changes in the

data line at this time will be interpreted as control signals. A

high to low transition of SDA with SCL high indicates a Start

condition, and a low to high transition of SDA whilst SCL is

high defines a Stop condition. The bus is considered to be

busy after a Start condition and free at a certain time interval

after a Stop condition. These conditions are always generated

by the Master.

Each byte is transmitted serially with the MSB first. The

byte is 8 bits long followed by an acknowledge bit. The clock

pulse related to the acknowledge bit is generated by the

Master. The device acknowledging must pull down the SDA

line during this clock pulse, whilst the transmitting device

releases the SDA line (pulled high) during this pulse. A Slave

receiver must generate an acknowledge after the reception of

each byte. If the receiving device cannot receive the data byte

immediately, it can force the transmitter to wait by holding the

SCL line low.

Each device on the bus has its own unique address. The

address of the microcontoller is fully programmable whereas

peripheral devices usually have fixed and programmable

portions. Before any data is transmitted on the bus, the

Master transmits on the bus the address of the Slave to be

accessed. The Slave should acknowledge the Master’s

addressing. The addressing is done by the first byte transmitted

by the Master after the start condition.

An address on the network is seven bits long, appearing as

the most significant bits of the address byte. The last bit is a

direction (R/W) bit, with a 0 indicating that the Master is

transmitting (WRITE) and a 1 indicates that the Master is

requesting data (READ). When an address is sent, each

device on the system compares the address with its own. If

there is a match the device will consider itself addressed and

send an acknowledge.

In addition to the above ‘standard’ addressing, the I2C bus

protocol allows for ‘general call’ addressing and interfacing to

CBUS devices. Fig. 19 shows a complete data transfer, comprised

of an address byte indicating a WRITE and two data bytes. It also

indicates the Start and Stop conditions .

Fig. 18 EXRESN reset

MRN I/P

100ms

EXRESN O/P

Associated Registers

REWD

A write access to this address will clear the watchdog 4-

second counter.

10. I2C INTERFACE

General

The ACE9050 I2C provides an interface between an I2C bus

and a microprocessor. Details of the I2C bus specification can be

found in the

Philips Components Technical Handbook.

The I2C bus allows integrated circuits to communicate directly

with each other via a bidirectional 2-wire bus. Interfacing the

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