ACE9050 datasheet(43/52 Pages) MITEL

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ACE9050

PORT5 Read/Write (Note 1)

Bits

5:4

OUT2.2_SEL

PWM1MUX

00 = OUT_PORT2[2] (Note 2)

01 = PWM2

10 = Latch 2

11 = Not valid

0 = PWM1

1 = OUT_PORT2[1] (note 2)

Name

Description

NOTES

1. These register bits are also described in the External Ports and

Multiplexer section.

2. Reset state.

Table 95

6. BEEP ALARM RING (BAR) TONE GENERATOR

TheACE9050providesaBeepAlarmandRingTonegenerator

unit. This provides a digital output pulse train. The high and low

time can be programmed with software. It is thus possible to vary

the output tone frequency, period and volume. The pulse train

can also be disabled whereupon the output will be set low. Within

the system this output can be used to control a buzzer driver.

External Pin

BAR Output (Pin 96)

CMOS output which is determined by the state of the registers

in the BAR block (BARHIGH, BARLOW and BARENABLE).

Associated Registers

Write

BARHIGH

BARLOW

BARENABLE

BAR ON time

BAR OFF time

0 = BAR output low

1 = BAR output pulsing

Description

Bits

7:0

Table 96

Programming

The two programmable 8-bit registers determine the ON and

OFF times in steps of approximately 8

µs (7·9µs). The maximum

ON and OFF times are approximately 2ms each (2·02ms). The

following formula is used to calculate the actual times:

BAR ON Time = (2562BARHIGH[7:0])37·93

µs

BAR OFF Time = (2562BARLOW[7:0])37·93

µs

7. KEYPAD INTERFACE AND CHIP IDENTITY

The Keyboard interface consists of a 5-bit output port, a 4-bit

input port and associated registers to read, write and configure

the ports (see Fig. 25).

Alternatively these ports can be used for general I/O. The

output port drive configuration can be set via software to provide

the system designer with full flexibility. The port has tristate

output buffers, controlled by the KPOT register. By programming

KEYP and KPOT appropriately the outputs can be configured to

drive in the following ways:

High impedance

Driving logic output (high or low)

Open drain

Open source.

[3:0]

KPI INPUTS

KEYP

WRITE

KEYP

READ

[7:4]

IDENT

KPOT

DATA BUS

KPO [4:0]

KPI [ 3:0]

59-55

66-69

010

Fig. 25 Keyport configuration

Output Port

The output port has five individual outputs, which can be used

as scanning outputs connected to a keyboard matrix, or can be

used for other general purposes .

External Pins

KP0[4: 0] Outputs (Pins 59: 55)

The state of these outputs are defined by the respective bits in

the internal registers KEYP and KPOT.

Associated Registers

KEYP Write

Keypad output port register

Description

Bits

4:0

Table 97

KPOT Write

Output Port driver configuration

Description

Bits

4:0

0 = Output driven to level set by relevant KEYP bit

1 = Output tristate

Sets or clears associated bit in Output Port register

Table 98

Programming Examples

The following bit patterns thus yield the following output

configurations:

KPOT

Output

Description

Logic drive

Open drain

Open source

High impedance

Table 99

KEYP

Write

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