ACE9050 datasheet(38/52 Pages) MITEL

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ACE9050

TXDATA

8-BIT SHIFT

LOAD

DATA 7:0

TXDATIN

MODPRT1

ENAMPI

MODPRT0

TXD REGISTER

IRQTX

DATA BUS

AMPS 100

µs

TACS 125

µs

CLOCK

Fig. 22 Modem Transmitter block diagram

WRITE 1st DATA

BYTE TO TXD

ENABLE ENAMPI

(1st DATA BYTE

TRANSMITTED)

WRITE 2nd DATA

BYTE TO TXD

WRITE 3rd DATA

BYTE TO TXD

(2nd DATA BYTE

TRANSMITTED)

WRITE LAST DATA

BYTE TO TXD

(LAST – 1

DATA BYTE

TRANSMITTED)

LAST DATA BYTE

TRANSMITTED

IRQTX

ENABLE

INTERRUPT

DISABLE

ENAMPI

Fig. 23 Modem transmission sequence

generating a square wave at the bit rate and EXORing the

generated clock with the relevant bit, for the bit period. The output

can then be inverted, if this is required by the system designer.

A block diagram is shown in Fig. 22.

No data manipulation is made by the encoder hardware. The

software must generate the dotting and Word sync patterns and

the BCH coding.

If the Transmitter is enabled the contents of the TXD register

will be transmitted on an IRQ-TX interrupt, regardless of whether

this register has been updated. This enables the generation of an

ST tone with no overhead on the processor, other than timing the

required duration. The software must simply write FFH or 00H to

the TXD.

Associated Registers (Tables 80, 81 and 82)

MODPRT2 This is a read/write port used for data transfer

Write

ENAMPI MODPRT 0 bit 3

Bit

TX output disabled

TX output enabled

Function

Bit

7:0 TXD[7:0] Data byte to transmit (bit 7 transmitted first)

Name

Function

Table 80

TXDINV MODPRT 1 bit 6

Bit

True Data output

Inverse Data output

Function

Table 81

Table 82

Data transmission sequence

Table 83 and Fig. 23 describe the correct sequence for

transmitting a Data message. Note that in the 5th step (Set

ENAMPI high quickly) the latency between the IRQ-TX and

setting ENAMPI will cause part of the first byte not to be

transmitted. This byte will always be part of a dotting sequence,

so this will not cause a degradation in data, however it is

desirable to reduce this time to a minimum.

Step

Enable IRQ-TX interrupt

Wait for IRQ-TX interrupt

Write Data byte to TXD

Wait for IRQ-TX interrupt

Set ENAMPI high quickly

Write Data byte to TXD

Wait for IRQ-TX interrupt

Repeat steps 6 and 7 until last byte

Write last byte

Wait for IRQ-TX interrupt

Disable ENAMPI

Action

Table 83 Modem transmission sequence

SAT MANAGEMENT

The SAT Management circuitry consists of a SAT detector,

SAT generator and a multiplexer. Refer to the External Pins

section of the General Description for details of the two external

pins: RXSAT and TXSAT .

SAT Detector

The SAT Detector measures the frequency of the signal on

RXSAT input. When the Modem is configured for a Voice

channel (VC_CCN high) a SAT measurement will occur every 10

to 12 ms. The SAT receiver measures the duration of 64 SAT

cycles and depending on the result determines the SAT value.

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