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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ACE9050 датащи(PDF) 16 Page - Mitel Networks Corporation |
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ACE9050 датащи(HTML) 16 Page - Mitel Networks Corporation |
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16 / 52 page  ACE9050 16 Bits [7: 4] [3: 2] [1: 0] Value XXXX 00 01 10 11 00 01 10 11 Not used Clock Control mode SCI disabled Use processor Clk for Baud rate Not used Use ACE 9050 Baud rate generator Speed Select (Bits 3: 2 = 01) E416 E4128 E41024 E44096 Description Table 18 RMCR Transfer Rate/Mode Control register mode is fully supported by the ACE9050 6303. This mode is entered by execution of the SLP instruction. Escape is via an interrupt or reset . Address, Data and Memory Control The Address, Data and control lines from the ACE9050 6303 connect to a kernel which interfaces to the on chip bus structures. The Bus Interface block provides suitable buffering to drive required buses externally, and configure the I/0 for Emulation mode. Interrupt Processing The interrupt processing in the ACE9050 6303 is essentially the same as a generic 6303, the exception being NMI, which is not available. The IRQN is internally connected to the I2C interrupt, the External Interrupt and the Internal interrupt blocks. These blocks combine all the possible sources for interrupts into one line which is connected to IRQN. This is also connected to a pin for use in Emulation mode. The IRQN is maskable. The interrupt mask bit in the Condition Code Register must be zero for the CPU to respond to the Interrupt request, as with a generic 6303. The Interrupt Vector Memory map is shown in Table 20. Error Processing An interrupt is generated when an undefined op-code is fetched, or when an instruction is fetched from an impossible address. This is in the range 0000- 007F for the ACE9050 (0000- 001F for a standard 6303). 2. INTERNAL ROM BOOT BLOCK The ROM code provides a boot block for the ACE9050. Following a reset condition code execution will always start in the internal ROM. The internal ROM data flow depends on the condition of the SERV Input and thus the mode of operation of the ACE9050. The operation flow of the IROM is shown in Fig. 12 and described in the following sections: Normal Mode 1. Read serial data on ACEBus DTFG line 2. Configure ACE9030 Reference dividers via ACEBus. 3. Set the program counter to the beginning of external ROM (1800H). Service Mode 1. Read serial data on ACEBus DTFG line 2. Configure ACE9030 Reference Dividers via ACEBus 3. Configure the UART to RX 4. Wait 2 seconds for special code on UART - if not found go to step 3 of Normal Mode 5. Load Data from UART into RAM Bits [7:0] (Data) [7:0] (Data) RDR: Received Data Register Read received bits. First bit received is placed in bit 0, last in bit 7 TDR: Transmit Data Register Write register to store bits before serial transfer from Transmit shift register, bit 0 first Description Table 19 Receive and Transmit Data registers In Normal Mode the SCI should be initialised before operation. This means writing to the mode select and the control/status register. In Service Mode the SCI is configured for 9600 baud, and the receive interrupt enabled. When the transmitter is first initialised it will send a ten-bit preamble of ‘1’s before being ready to transmit data. Once initialisation is complete data transmission enabled by writing to the transmit data register. TDRE is set to 0. A start bit is transmitted (0). Next the eight bit data starting at bit0 are transmitted followed by a single stop bit (1). The hardware sets the TDRE bit in the TRCSR register. If the CPU does not transfer another word the output goes high. The receiver is configured during initialisation. If enabled and a start bit is detected (0), the next nine bits will be sampled approximately at the centre of each bit. If the ninth bit is a 1 the data is transferred to the Receive data register. The RDFR bit is set in the TRCSR register. If the ninth bit is not a 1 or the receive data register is full then the ORFE bit is set to indicate an error. A read of the TRCSR register followed by a read of the Received data register (RDR) will clear these flags. RAM Control Register (RAMCR) This register is read only in the ACE9050. Bit 6 (RAME) is set to zero: this is because the RAM on the ACE9050 is external to the 6303 block. Bit 7 (STBY) is also set to zero by the ACE9050 because Standby mode is not supported. Operating Modes The Generic 6303R has two modes: Multiplexed and non- Multiplexed, where the mode is selected externally using P2[0], P2[1] and P2[2]. This is not required on the ACE9050, where the mode is set to mimic multiplexed internally when the reset (MRN) is released . The ACE9050 processor has two fundamental modes of operation: Emulation and Normal, which are described in the MODES OF OPERATION section. Low Power Consumption Modes The generic 6303 Standby mode is not supported by the ACE9050 6303. The STBY pin is not accessible. The Sleep Priority 1 2 3 4 5 6 7 8 MSB FFFE FFEE FFFA FFF8 FFF6 FFF4 FFF2 FFF0 LSB FFFF FFEF FFFB FFF9 FFF7 FFF5 FFF3 FFF1 Interrupt Vector RES TRAP Software Interrupt (SWI) IRQN ICF (Timer Input Capture) OCF (Timer OP Compare) TOF (Timer Overflow) SCI (UART) Table 20 Interrupt vector memory map |
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