ACE9050 datasheet(29/52 Pages) MITEL

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ACE9050

Position

State

Bit

If a repeated START condition has been transmitted then the

status code will be 10H instead of 08H.

2. Transmit Slave Address and Write The I2C_DATA register

should now be loaded, with the address of the slave to be written

to in bits[7:1] and bit[0] cleared to zero to specify Write. The IFLG

bit should now be cleared to zero before the transfer can

continue. When the slave address and write bit have been

transmitted and an acknowledqe bit received the IFLG will be set

again. A number of status codes are now possible in the STAT

3. Transmit Data If the code 18H or 20H has been detected in the

STAT, the next byte to be placed in the I2C_DATA register is the

first data byte, or a word address in the case of some memory

devices. The IFLG can then be cleared. After each additional

data byte has been transmitted the IFLG will be set and one of

three status codes will be in the START register, as shown in

Tables 49 and 50.

IEN

ENAB

STA

STP

IFLG

AAK

Table 46

1. Transmit Start Condition. The master transmit mode is

entered by settinq the STA bit to one. The ACE9050 I2C will then

test the I2C bus and will transmit a START condition when the bus

is free. When a START condition has been transmitted the IFLG

bit will be set and the status code in the STAT register will be 08H.

Transmit data byte,receive ACK

Transmit repeated START

Transmit STOP

Transmit STOP then START

As for code 18H

(a) WriteDATA, clear IFLG

(b) Set STA, clear IFLG

(d) Set STA and STP, clear IFLG

As for code 18H

Addr and Write transmitted, ACK received

Addr and Write transmitted, ACK not received

18H

20H

Next I2C action

Micro response

ACE9050 I2C state

Code

(a) Clear IFLG

(b) Set STA, clear IFLG

Clear IFLG: AAK = 0

Clear IFLG: AAK = 1

As for code 68H

Write byte to DATA, clear IFLG, AAK = 0

Write byte to DATA, clear IFLG, AAK = 1

38H

68H

78H

B0H

Next I2C action

Micro response

ACE9050 I2C state

Code

Arbitration lost

Arbitration lost, Slave Addr and

Write received: ACK transmitted

Arbitration lost, GCA, ACK transmitted

Arbitration lost, Slave Addr and

Read received: ACK transmitted

Transmit data byte,receive ACK

Transmit repeated START

Transmit STOP

Transmit START then STOP

As for code 28H

(a) Write byte to DATA, clear IFLG

(b) Set STA, clear IFLG

(d) Set STA and STP, clear IFLG

As for code 28H

Data byte transmitted, ACK received

Data byte transmitted, ACK not received

28H

30H

Next I2C action

Micro response

ACE9050 I2C state

Code

Return to idle

Transmit START when bus free

(a) Clear IFLG

(b) Set STA, clear IFLG

Arbitration lost

38H

Next I2C action

Micro response

ACE9050 I2C state

Code

Table 49 Possible status codes after Data has been transmitted with the ACE9050 as the only bus Master

Table 47 Possible status codes after Slave address has been transmitted with the ACE9050 as the only bus Master

Table 48 Possible status codes after Slave address has been transmitted with Multiple Bus Masters

Table 50 Possible extra status codes after Data has been transmitted with multiple bus Masters

Return to idle.

Transmit START when bus free.

Receive data byte, transmit Not ACK

Receive data byte, transmit ACK

As for code 68H

Transmit last byte, receive ACK

Transmit data byte, receive ACK

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