ACE9050 datasheet(22/52 Pages) MITEL

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ACE9050

Fig. 16 ACE9050 Interrupt configuration

IRQPRT4

RESET

TIME OUT

IRQSEND

IRQREQ

IRQRX

IRQBISAT

IRQWS

IRQTX

LATCHING

LOGIC

IRQPRT5

MASK

DATA BUS

IRQPRT2

READ

AND

COMBINING

LOGIC

IRQPRT0

RESET

IRQPRT1

MASK

DATA BUS

LATCHING

LOGIC

IRQPRT6

READ

AND

COMBINING

LOGIC

PORT1

INPUT

DATA BUS

I2C

INTERRUPT

IRQN

INRQ0

INRQ1

INP1 [2]

INP1 [3]

INP1 [4]

SERV

TXPOW

ACE9050

TO 6303

External Interrupt Control Port

The external interrupt control port facilitates resetting, masking

and reading of two potential external interrupt sources via three

registers. The external interrupt inputs are edge sensitive. Table

31 describes the possible sources

Bit

INRQ1

INRQ0

External Interrupt 1 (INRQ [1])

External Interrupt 0 (INRQ [0])

Name

Description

Table 31

External pins

INRQ0 (pin 71)

A rising edge (zero to one transition) on this line will generate

an INRQ0 interrupt if the associated bit in the mask register is set

to 1. The level of this input can also be read via Port1 bit 0

regardless of whether an interrupt is generated.

INRQ1 (pin 70)

A rising edge (zero to one transition) on this line will generate

an INRQ1 interrupt if the associated bit in the mask register is set

to 1. The level of this input can also be read via Port1 bit 1

regardless of whether an interrupt is generated.

Associated Registers (Table 32)Bit7: 0

IRQPRT4: External Interrupt Reset Register. A write to this

data field.

IRQPRT5: External Interrupt Mask Register. A write to this

reset all interrupts are masked.

IRQPRT6: External Interrupt Read register. A Read from this

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