ACE9050 datasheet(39/52 Pages) MITEL

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ACE9050

Further software filtering may be required. The result of the

measurement will reside in MODPRT1 bits 5 and 6. If the IRQ-

BI-SAT interrupt is not masked an IRQ-Bl-SAT interrupt will

occurattheendofeachmeasurementperiod,aftertheMODPRT1

has been updated.

Associated Register

SCCRX [1:0] MODPRT1 [5:4]

Read

SCCRX [1:0]

5955-5984

5985-6014

6015-6045

< 5955 > 6045

Limits (Hz)

SAT tone (Hz)

5970

6000

6030

No SAT

Table 84

SAT Transmitter

The ACE9050 has an on-chip SAT generator which can

generate 5·97kHz, 6kHz, or 6·03 kHz signals. The selection is

made via bits SCCTX [1:0] in MODPRT0. Alternatively the

received SAT can be looped around and re-transmitted. The

ACE9050 provides a multiplexer so either source can be selected

under software control via the SATMUX bit in PORT4.

The generator circuit consists of a series of preset counters

runningfromthesystemclock.TheACE9050makesnoallowance

for varying the phase of the regenerated SAT tone as this not a

requirement for current AMPS or TACS protocols.

When the Received SAT is looped around the ACE9050 only

buffers the incoming SAT signal on RXSAT before feeding it to

the TXSAT output pin.

Associated Registers

SCCTX[1:01 MODPRT0 [5:4]

Write

SCCTX [1:0]

Generated SAT tone (Hz)

5970

6000

6030

No SAT generated

Table 85

SATMUX PORT 4[2]

SATMUX

Internally generated SAT

RX SAT

TX SAT source

Table 86

The buses can be used for data transfer between any ICs that

have the appropriate interface logic; however, in a system using

the ACE Chips the following words are valid on the ACEBus:

ACE9030

Sleep Word

Normal (ADC Values Read)

Set-up

Synth Word A

Synth Word B

Synth Word C

Synth Word D

Synth Dummy word (Low Noise Mode)

ACE9040

Operating mode

Initialising Mode 0

Initialising Mode 1

Handsfree

For more information refer to the ACE9030 and ACE9040

data sheets.

The ACEBus consists of a 1·008MHz clock, a bidirectional

data line and 4 latch outputs. The clock and data lines are

common, while the latch outputs are connected as follows:

Latch 0: Control (ACE9040, LEN)

Latch 1: Radio interface section (ACE9030, LATCHB)

Latch 2: Internally connected to MUX #2

Latch 3: Synthesiser section (ACE9030, LATCHC)

Valid data is transmitted in a stream of 24 continuous bits. At

the end of the last bit the relevant latch is activated. This will latch

the data into the target device. The data line will become tristate

after the data transfer so that data may be received from a bus

driver.

The block contains eight ACE9050 registers. Three are for

serial data transmit, three for receive and two are for bus control.

The block also contains interrupt generating circuitry. The

SynthBus contains a data line Synthdata, clock line Synthclk and

associated Latch2, which is multiplexed with OUT2[2] and

PWM2.

The clock to ACE Serial Interface block can be disabled to

reduce the overall power consumption of the ACE9050. Turning

off this clock will disable the ACE Serial Interface but will not turn

off the C1008 clock.

External Pins

3. ACE SERIAL INTERFACE BLOCK

General Description

The ACE Serial Interface contains two serial interfaces: The

ACEBus and the SynthBus. The ACEBus is used to distribute

data to and from ICs in the ACE chipset. The SynthBus is

redundant when using the ACE chipset.

The ACE9050 contains the Master Transmitter/Receiver unit

for the ACEBus. The ACE9040 and ACE9030 contain slave

units. The bus is used for programming the devices into the

required state. This will be required when the phone is powered

up, and during phone operation. The ACE9030 can also transmit

ADCs values to the ACE9050 on the ACEBus.

C1008 (pin 90)

Refer to Clock Generator Section. This clock is used for data

transfer. In the ACE9030 and ACE9040 it is also used for

clocking other functions so care must be exercised in turning this

clock off.

DTFG (pin 82)

Bidirectional data line. The ACE9050 clocks out data loaded

into the 3 registers. Data is clocked in and out of the ACE9050

on the falling edge of C1008.

LATCH 0 (pin 80)

Latch pulse used to target data transfer. In a system using the

ACE chip set Latch0 is connected to the LEN input of the

ACE9040. The latch is nominally a 500ns pulse.

LATCH 1 (pin 78)

Latch pulse used to target data transfer. In a system using the

ACE chip set Latch1 is connected the ACE9030 Radio Interface

(LATCHB). The latch is nominally a 500ns pulse.

LATCH 3 (pin 75)

Latch pulse used to target data transfer and optimise the

performance of the synthesiser. In a system using the ACE chip

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