ACE9050 datasheet(40/52 Pages) MITEL

40 / 52 page

ACE9050

set Latch3 is connected to the LATCHC input of the ACE9030

Synthesiser. The lenqth of the latch can be varied and the latch

can be set permanently high. Latch 3 can be used with the

SynthBus, but is fixed at 500ns.

SYNTHCL (pin 73)

SynthBus clock line at nominally 126kHz. This is not a

continuous clock. It is only activated when data transfer is

required.

SYNTHDAT (pin 72)

SynthBus Data line. Contains valid data from the ACE9050,

or is set to zero.

Transmitter Section

The transmitter consists of five write registers, interrupt and

latch generating logic, clock divider and timer, and three shift

registers connected in series. These form the 24-bit message

that is sent out on DTFG. The most significant bit of LSICOM 0

is transmitted first (refer to Fig. 7).

Associated Registers

Write

LSICOM 0

LSICOM 1

LSICOM 2

First byte to transmit

Second byte to transmit

Third byte to transmit

Description

Bits

7:0

Table 87

SINTSLEEP Port 4 [7]

Bit

Function

0 = ACE Serial Interface enabled

1 = ACE Serial Interface powered down

Name

SINTSLEEP

Table 88

STR_WIDTH Write

The pulse width of Latch 3 is programmable between 99·2

µs

and 12·6ms, with 99·2

µs increments. This register only works

with the ACEBus, not the Synthbus.

Description

Bits

Table 89

LSICOM 3 Write

This register is the control register. This is used to define the

mode of the data transfer, select which latch to activate and also

is used to initiate the transfer.

Bit

Name

Function

6:0

Pulse duration in increments of 100 C1008 periods.

This register is decremented when a pulse is

generated. Writing a value of 0 in this register

terminates the pulse.

0 = No data transfer

1 = Begin data transfer

Must be 1

0 = No Answer request

1 = Answer request

Must be 0

ANS

Not used

Receiving Data

In order to receive, LSICOM 3[5] (ANS) must be set. After the

transmission sequence, data on the DTFG line is clocked into the

receiver on the falling edge of C1008. This process begins on the

fifth negative clock edge after the latch pulse, to allow a response

time from the slave (Fig. 8).

After 24 clock cycles the complete word will have been

clocked into the ACE9050. The data in the shift registers is

latched into the three read registers. At the same time the IRQ-

REC interrupt is generated.

The IRQ-SEND interrupt is generated in the receive sequence

with the relevant latch in the same way as for a transmit only

sequence.

Receiver Section

The receiver consists of three serial registers which can be

read via LSICOM 4, 5 and 6. It also contains a counter, clocking

and interrupt generating circuitry.

Associated Registers

Read

LSICOM 4

LSICOM 5

LSICOM 6

First byte received (ACE9030 preamble)

Second byte received (ACE9030 result 1)

Third byte received (ACE9030 result 2)

Description

Bits

7:0

Table 92

Sending Data

To begin the transmitting sequence the appropriate word has

to be written to LSICOM 3. If a Latch 3 is required for the ACEBus

a non-zero value must be written to STR_WIDTH prior to writing

the control word in LSICOM 3.

When LSICOM 3[7] (GO) is set, the clock to the serial shift

registers is enabled. Data from LSICOM 0, 1 and 2 are clocked

out on the falling edge of C1008. After the 24 data bits have been

clocked out, the appropriate latch is generated on the next fallinq

edge of C1008. At the same time as the latch the IRQ-SEND

interrupt is generated internally. This is fed to the interrupt control

block where it can be masked. The LSICOM 3 will then be reset,

so as to be ready for the next data transfer.

Table 90 Valid bit fields for ACEBus data transfer

Bit

Name

Function

Must be 0

Latch 1 enabled for data transfer

Latch 0 enabled for data transfer

Not used

Latch 1

Latch 0

Table 90 (continued)

Bit

Name

Function

0 = No data transfer

1 = Begin data transfer

Must be 0

Latch 3 enabled for data transfer

Latch 2 enabled for data transfer

Must be 0

Not used

Latch 3

Latch 2

Not used

Table 91 Valid bit fields for SynthBus

LSICOM 3 (continued)

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