ACE9050 datasheet(26/52 Pages) MITEL

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ACE9050

SDA

SCL

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

· · · · ·D1

1-7

STOP

CONDITION

START

CONDITION

· · · · ·D1

Fig.19 I 2C Data transfer

ACE9050 I2C

The ACE9050 I2C can operate in one of four modes:

1. Master Transmit

2. Master Receive

3. Slave Transmit

4. Slave Receive

The ACE9050 can operate in multi-Master systems (where

there is more than Master on the bus). The ACE9050 I2C will

perform bus arbitration and clock synchronisation. In a mobile

handset where the I2C is used to interface to a serial PROM and/

or an LCD display it would be sufficient to have the ACE9050 as

the sole Master.

The I2C interface consists of the SCL (clock) and SDA (data)

lines. These are multiplexed with the 6303 bidirectional Port1

pins to reduce the overall pin count. Selection is made via the

ACE9050 Port5.

The internal 6303 microprocessor interface consists of five 8-

bit memory mapped registers and a processor interrupt line. The

interrupt is connected to the 6303 IRQN interrupt, as are the

ACE9050 internal and external Interrupt ports.

External Pins

SCL/6303 Port 1 [4] (pin 9)

Bi-directional pin, used for the I2C clock when selected. This

pin requires an external pull up resistor when used as SCL.. The

value of the pull up resistor depends on the system and I2C bus

implementation. Refer to the I2C bus specification. In a typical

system the resistor value would fall between 1k

Ω and 20kΩ.

SDA/6303 Port 1 [3] (pin 13)

Bidirectional pin, used for the I2C data when selected. This pin

requires an external pull up resistor when used as SDA. The

value of the resistor should be the same as the SCL line.

Associated Registers

SEL_I2C Port 5 bit 2

Position

IEN

ENAB

STA

STP

IFLG

AAK

Bit

Description

Table 40

Interrupt Enable

Bus Enable

Master Mode Start

Master Mode Stop

Interrupt Flag

Assert Acknowledge

Read back only: 0

I2C_CNTR Control Register Read/Write

This register is used to control the ACE9050 I2C. The program

can write and read from the register. The hardware can also

change the status of the bits in this register (see Table 40).

Note that this register is cleared to 00H when the I

2C is reset.

IEN Interrupt Enable

When IEN is set to 1 an interrupt will occur when the IFLG bit

is set. This will cause an interrupt on the 6303 IRQ. When IEN is

cleared to zero the I2C interrupt will be disabled.

Bit

SEL_I2C 0 = I2C Reset, P1 [4] and [3] selected

1 = I2C operational, SCL and SDA selected

Name

Description

Table 39

ENAB Bus Enable

When ENAB = 1 the ACE9050 I2C will respond to calls to its

Slave address (SLA6-0) and to the general call address if bit

GCE in the I2C_ADDR register is set.

STA Start Master Mode

When STA = 1 the ACE9050 I2C enters Master mode and will

send a START condition on the bus when the bus is free. If the

STA bit is set to 1 when already in Master mode and one or more

bytes have been transmitted then a repeated START condition

will be sent. If the STA bit is set to 1 when the ACE9050 I2C is

being accessed in Slave mode then the ACE9050 I2C will

complete the data transfer in Slave mode and then enter Master

mode when the bus has been released.

After the START condition has been sent this bit will be

automatically cleared.

STP Stop Master Mode

When STP is set to 1 in Master mode then a STOP condition

is transmitted on the I2C bus. If the STP bit is set to 1 in Slave

mode then the ACE9050 I2C will behave as if a STOP condition

has been received, but no STOP condition will be transmitted on

the I2C bus. If both STA and STP bits are set the ACE9050 I2C

will first transmit the STOP condition (if in Master mode) then

transmit the START condition. The STP bit is automatically

cleared: writing a zero to this bit has no effect.

IFLG Interrupt Flag

This bit gets set if an interrupt condition occurs in the I2C;

however an interrupt will only be generated if the Interrupt Enable

(IEN) is set.

An interrupt condition is defined as one of 26 of the possible

27 ACE9050 I2C states being entered. The only state that does

not set IFLG is state F8H. Refer to STAT register for more

information on the I2C states.

When IFLG is high then the low period of the I2C bus clock line,

SCL, is stretched and the data transfer is suspended.

When IFLG is reset to zero the interrupt is reset and the I2C

clock line released.

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