ACE9050 datasheet(31/52 Pages) MITEL

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ACE9050

4. Transmit Stop When the Master has finished receiving data

it must signal the end of data to the Slave transmitter by

generating a not acknowledge on the last byte that was clocked

out by the Slave. The Slave transmitter must release the data line

to allow the Master to generate the STOP condition. When all

bytes have been received the I2C_STAT register should return

a 58H. The microcontroller is then free to set the STP bit. The

ACE9050 I2Cwill transmit a STOP condition, clear the STP bit

and return to the idle state.

Slave Transmit

In the Slave transmit mode a number of bytes are transmitted

to a Master receiver. The Slave transmitter has control of the

SDA line and must ensure the bits are correctly acknowledged.

Before the Slave transmit mode can be entered the CNTR

either 0 or 1.

Slave Receive

In the Slave receive mode a number of data bytes are

received from a Master transmitter. Before the Slave receive

mode can be entered the CNTR register should be initialised as

for Slave transmit mode.

1. Entering Slave Receive Mode The ACE9050 I2C will enter

Slave receive mode when it receives its own Slave address

(SLA6-0) and the write bit (bit = 0) after the START condition. The

ACE9050 I2C will then transmit an acknowledge bit and set the

IFLG bit in the I2C_CNTR register and status code 60H (Slave

address1write bit received, ACK Transmitted) will be in the

STAT register.

The ACE9050 I2C will also enter Slave receive mode when it

receives the general call address 00H (if bit GCE in the ADDR

Slave receive mode can also be entered directly from a

Master mode if arbitration was lost in Master mode during the

address byte, and the Slave address and write bit or general call

address were received. (For the general call condition the GCE

bit in the I2C_ADDR register must be set to one)

The status code in the I2C_STAT register will then be 68H if

the Slave address was received or 78H if the general call address

was received. The IFLG bit must be cleared to zero to allow the

data transfer to continue.

2. Receiving Data If the AAK bit in the I2C_CNTR register is set

to 1 then after each byte is received an acknowledge bit (low level

on SDA) is transmitted and the IFLG bit is set, the I2C_STAT

was entered with the general call address). The received data

byte can be read from the I2C_DATA register and the IFLG bit

must be cleared to allow the transfer to continue.

3. Competing Transfer When the STOP condition or a repeated

START condition is detected after the acknowledge bit, then the

IFLG bit is set and the I2C_STAT register will contain status code

A0H. If the AAK bit is cleared to 0 during a transfer then the

ACE9050 I2C will transmit a not acknowledge bit (high level on

SDA) after the next byte is received, and set the IFLG bit. The

I2C_STAT register will contain status code 88H (or 98H if slave

receive mode was entered with the general call address). When

the IFLG bit has been cleared to 0 the ACE9050 I2C will return

to the idle state.

Position

State

Bit

IEN

ENAB

STA

STP

IFLG

AAK

Table 55

1. Entering Stave Transmit Mode The ACE9050 I2C will enter

Slave transmit mode when it receives its own Slave address

(SLA6-0) and the read bit (bit 0 = 1 ) after a START condition. The

ACE9050 I2C will then transmit an acknowledge bit and set the

IFLG bit in the I2C_CNTR register and status code A8H (Slave

address and read bit received, ACK transmitted) will be in the

I2C_STAT register.

Slave transmit mode can also be entered directly from a

Master mode if arbitration was lost in Master mode during the

address byte, and the Slave address and read bit were received.

The status code in the I2C_STAT register will then be B0H.

2. Sending Data The data byte to be transmitted should then be

loaded into the I2C_DATA register and the IFLG cleared. When

the ACE9050 I2C has transmitted the byte and received an

acknowledge the IFLG will be set and the STAT register will

contain B8H.

3. Completing Transfer Slave Termination When the last byte

to be transmitted is loaded into the DATA register the AAK bit

should be cleared when, or immediately before the IFLG is

cleared. After that last bit has been transmitted the IFLG will be

set as usual but the STAT should contain C8H.

When this IFLG flag is cleared the ACE9050 I2C will then

return to the idle state. The AAK bit must be set to one before

Slave mode can be entered again.

4. Master Termination If no acknowledge is received after

transmitting any byte: the SDA line is released to allow the

Master to generate, the Stop condition IFLG will be set and the

STAT register will contain C0H. When the IFLG is cleared the

ACE9050 I2C will return to the idle state. If the STOP condition

is detected after an acknowledge bit then the ACE9050 I2C will

return to the idle state.

RADIO FUNCTIONS

The ACE9050 provides the following Radio Functions, which

will typically be required in a mobile phone implementation, all of

which are controlled by internal configuration registers:

Modem and SAT management,

ACE Serial Interface,

IFC counter,

2 pulse width modulators,

Key pad interface and

Tone generator.

These functions are described in the following sections

1. INTERNAL CONFIGURATION REGISTERS

The ACE9050 contains 3 internal configuration registers.

These allow the hardware to be configured via software write

instructions. The function of the bits is described in the relevant

section in more detail. This section provides an overview of the

3 internal configuration registers.

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