ACE9050 datasheet(45/52 Pages) MITEL

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ACE9050

Block Descriptions

ATO Timer

The ATO timer is a 30 second resetable counter. If the ATO

counter reaches 30 seconds, an ATO Reset is generated. The

counter is reset by the following actions:

(a) External MRN Reset

(b) Accepted Processor Write to the RESATO register

The levels of the two external signals RXCD (pin 100) and

TXPOW (pin 61) are used to determine whether a processor

Write to RESATO is accepted or not, as shown in Table 106.

RXCD

Accepted

Denied

Accepted

RESATO access

TXPOW

NOTE: The CPU cannot tell whether a hardware access has been

accepted or not.

Table 106

The RXCD input is filtered prior to use in the ATO Timer logic

by the RXCD Filter.

The ATO timer is NOT reset by Watchdog reset.

ATO Reset

When the AT0 Times Out the ATO reset circuit is trigered and

the following occurs:

(a) A Time Out Interrupt is generated.

(b) If the POFFN is high it will be driven low.

The Time Out interrupt is generated at least 1 second before

the POFFN is driven low. This is to give the processor time to

clean up before power is removed. The processor cannot

prevent the ATO reset at this stage.

The ACE9050 design assumes that the ATO Reset will

remove power from the phone system. If the system is designed

in such away that power is not removed from the ACE9050 the

POFFN pin is only guaranteed to stay low for approximately 1

second. The state of the internal circuitry is not guaranteed after

an ATO Reset.

RXCD Filter

The purpose of the filter is to smooth out short glitches in the

RXCD input. The filter waits for 1 second of RXCD becoming

high before the filter output is asserted. Once the output has been

asserted for more than 1 second, if the RXCD goes low for more

that 1 second the filter output will go low.

The filter hardware consists of a 10-bit up-down counter

clockedat492Hz.IftheRXCDinputishighthecounterincrements.

If it is low the counter decrements. Thus, assuming the counter

begins at zero, with a fixed high on the RXCD the counter’s MSB

will assert after 1 second and will overflow after approximately 2

seconds. When the counter overflows and RXCD is high it will

continue to hold the maximum count value and conversely, when

it reaches zero and RXCD is low, it will contain zero. The MSB

of the counter is the filter output which is fed to the ATO.

Programming Guide

Although the processor only needs to access the ATO

should occur more frequently. This would ensure a spurious

error condition unfortunately timed would not cause an ATO turn-

off. Servicing the ATO with the Watchdog would be the sensible

approach.

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