ACE9050 datasheet(19/52 Pages) MITEL

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ACE9050

AS Address Strobe (pin 5)

This input is used in Emulation Mode only. Th external D [7:0] will

contain both data and the lower 8 bits of the address bus.The Bus

Interface provides the transparent latch required to hold the

value of the address during the latter part of the cycle. The AS is

provided to control the Latch Enable. In a typical system this will

be directly connected to the emulating 6303 AS output.

R/W Read/Not Write (pin 95)

This is an output in Normal mode, but an input in Emulation

Mode. It is the processor Read/Not Write line. The timing of this

output is not guaranteed to be the same as a standard 6303

processor. In Emulation mode it will be directly connected to the

Emulating 6303 R/W line.

D [7:0] Data (and Address in Emulation mode) (Pins 18-25)

In Normal mode these pins provide bidirectional data transfer

between the ACE9050 6303 and external memory. In Emulation

mode they provide the directional data and the lower 8 bits of the

address bus into the ACE9050.

A [7:0] Lower 8 address bits (Pins 40, 39, 35-30)

These outputs provide the lower 8 bits of the address bus for

external memory. This is the case for both Normal and Emulation

modes.

A [13:8] Address Bits 13 to 8 (pins 46-41)

In Normal mode these provide the output of the ACE9050

6303 address bus bits 13 to 8, for addressing external devices.

In Emulation mode, A[13:8] provide input for an external 6303

address bus, to address the ACE9050 functions excluding the

6303.

A [15:14] Emulation Address bits 15 and 14 (pins 92 and 93)

These inputs are only used in Emulation mode. The

internal 6303 address A[15:14] are fed to the banked address

logic and not to an external pin. In emulation mode the host

processor must drive the complete 6303 internal address bus

so A[15:14] inputs are provided. The host processor will then

drive the entire internal bus and the bank select register, so

the external memory access will be the same regardless of

Emulation or Normal mode.

BA [17:14] Banked address (pins 50 to 47)

The ACE9050 expands the external address bus to 18 bits.

This allows up to 256K of memory space. BA [17:14] are the

outputs from the bank select register. The operation of the

refister is described further in ‘Memory Map and Banked

Addressing’, below.

CSEPN Chip Select (pin 28)

This output provides active low chip select for accessing

external program memory. On reset the entire external memory

address space is mapped to CSEPN. In the Banked area of the

memory map the programmer can select either CSEPN or

CSE2N access via bit 4 of the Bank Select register.

CSE2N Chip Select (pin 29)

This output provides an active low chip select for accessing

external memory or other suitable device. In the Banked area of

the memory map the programmer can select either CSEPN or

CSE2N access via bit 4 of the Bank Select register.

VDDM Supply to Memory Interface (pin 38)

The power supply

pin for the memory interface, VDDM,

provides the power supply for the following pads:

A [13:0], BA [17:14], D [7:0], CSEPN, CSE2N, WEN and OEN

Memory Map and Banked Addressing

The ACE9050 provides the circuitry to create a banked

addressingsystemwhichwillincreasethesizeoftheprogramming

space from 16 bit (64K bytes) to 18 bit (256K Bytes) and enable

two Chip Select lines to be programmed. This is achieved using

an internal register to select the required page of memory and

chip select line.

The use of banked addressing and associated circuitry is not

mandatory in a system using an ACE9050.

When using banked addressing the external addresses

generated and thus the system memory map are different from

the 6303 memory map. The banked addressing functions in the

same manner for both Normal and Emulation mode with a

external processor.

Fig. 13 Data and Address bus configuration

ACE9050 6303

AND KERNEL

ID[7:0] (DISABLED IN EMULATION MODE)

AD[15:0]

IRW







(DISABLED IN EMULATION MODE)

TRANSPARENT

LATCH

MEMORY

BANK

SWITCHING

INTERNAL

ADDRESS BUS [15:0]

NORMAL:

EMUL:

NORMAL:

EMUL:

[7:0]

[13:8]

[15:14]

DATA BUS

INTERNAL EPROM

CHIP SELECT

[15:14]

LATCH ENABLE

A[13:8] OUTPUT

A[13:8] INPUT

NOT USED

A[15:14] INPUT

A[7:0]

BA[17:14]

CSEPN

CSE2N

NORMAL:

EMUL:

R/W NOT USED

R/W INPUT

NORMAL:

EMUL:

NOT USED

AS INPUT

NORMAL:

EMUL:

D[7:0]

D[7:0] & A[7:0] INPUT

INTERNAL

READ / NOT WRITE

INTERNAL

DATA BUS [7:0]

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