PIC17C752-08SLASHCL datasheet(136/328 Pages) MICROCHIP

136 / 328 page

PIC17C7XX

DS30289A-page 136

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. Buffer

full bit, BF (SSPSTAT<0>), indicates when SSPBUF

has been loaded with the received data (transmission

is complete). When the SSPBUF is read, bit BF is

cleared. This data may be irrelevant if the SPI is only a

transmitter. Generally the MSSP Interrupt is used to

determine when the transmission/reception has com-

pleted. The SSPBUF must be read and/or written. If the

interrupt method is not going to be used, then software

polling can be done to ensure that a write collision does

not occur. Example 15-1 shows the loading of the

SSPBUF (SSPSR) for data transmission.

EXAMPLE 15-1: LOADING THE SSPBUF

(SSPSR) REGISTER

The SSPSR is not directly readable or writable, and can

only be accessed by addressing the SSPBUF register.

Additionally, the MSSP status register (SSPSTAT) indi-

cates the various status conditions.

MOVLB 6

; Bank 6

LOOP BTFSS SSPSTAT, BF

; Has data been

;

received

;

(transmit

;

complete)?

GOTO

LOOP

; No

MOVPF SSPBUF, RXDATA ; Save in user RAM

MOVFP TXDATA, SSPBUF ; New data to xmit

15.1.2

ENABLING SPI I/O

To enable the serial port, MSSP Enable bit, SSPEN

(SSPCON1<5>) must be set. To reset or reconﬁgure

SPI mode, clear bit SSPEN, re-initialize the SSPCON

registers, and then set bit SSPEN. This conﬁgures the

SDI, SDO, SCK, and SS pins as serial port pins. For the

pins to behave as the serial port function, some must

have their data direction bits (in the DDR register)

appropriately programmed. That is:

• SDI is automatically controlled by the SPI module

• SDO must have DDRB<7> cleared

• SCK (Master mode) must have DDRB<6> cleared

• SCK (Slave mode) must have DDRB<6> set

•SS must have PORTA<2> set

Any serial port function that is not desired may be over-

ridden by programming the corresponding data direc-

tion (DDR) register to the opposite value.

15.1.3

TYPICAL CONNECTION

Figure 15-8 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge, and latched on the opposite edge

of the clock. Both processors should be programmed to

same Clock Polarity (CKP), then both controllers would

send and receive data at the same time. Whether the

data is meaningful (or dummy data) depends on the

application software. This leads to three scenarios for

data transmission:

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

• Master sends dummy data — Slave sends data

FIGURE 15-8: SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb

LSb

SDO

SDI

PROCESSOR 1

SCK

SPI Master SSPM3:SSPM0 = 00xxb

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave SSPM3:SSPM0 = 010xb

Serial Clock

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