PIC17C752-08SLASHCL datasheet(135/328 Pages) MICROCHIP

135 / 328 page

DS30289A-page 135

PIC17C7XX

15.1

SPI Mode

The SPI mode allows 8-bits of data to be synchro-

nously transmitted and received simultaneously. All

four modes of SPI are supported. To accomplish com-

munication, typically three pins are used:

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Serial Clock (SCK)

Additionally a fourth pin may be used when in a slave

mode of operation:

• Slave Select (SS)

15.1.1

OPERATION

When initializing the SPI, several options need to be

speciﬁed. This is done by programming the appropriate

control

bits

the

SSPCON1

(SSPCON1<5:0>) and SSPSTAT<7:6>. These control

bits allow the following to be speciﬁed:

• Master Mode (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data input sample phase

(middle or end of data output time)

• Clock edge

(output data on rising/falling edge of SCK)

• Clock Rate (Master mode only)

• Slave Select Mode (Slave mode only)

Figure 15-7 shows the block diagram of the MSSP

module when in SPI mode.

FIGURE 15-7: MSSP BLOCK DIAGRAM

(SPI MODE)

The MSSP consists of a transmit/receive Shift Register

(SSPSR) and a BUFfer register (SSPBUF). The

SSPSR shifts the data in and out of the device, MSb

ﬁrst. The SSPBUF holds the data that was written to the

SSPSR, until the received data is ready. Once the

8-bits of data have been received, that byte is moved to

the SSPBUF register. Then the buffer full detect bit BF

(SSPSTAT<0>) and the interrupt ﬂag bit SSPIF

(PIR2<7>) are set. This double buffering of the

received data (SSPBUF) allows the next byte to start

reception before reading the data that was just

received. Any write to the SSPBUF register during

transmission/reception of data will be ignored, and the

write collision detect bit WCOL (SSPCON1<7>) will be

set. User software must clear the WCOL bit so that it

can be determined if the following write(s) to the SSP-

BUF register completed successfully.

Read

Write

Internal

data bus

SSPSR reg

SSPBUF reg

SSPM3:SSPM0

bit0

shift

clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 output

TOSC

Prescaler

4, 16, 64

Edge

Select

Data to TX/RX in SSPSR

Data direction bit

SMP:CKE

SDI

SDO

SCK

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