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RM0319 датащи(PDF) 278 Page - STMicroelectronics |
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RM0319 датащи(HTML) 278 Page - STMicroelectronics |
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278 / 368 page ![]() LCD display controller (CLCD) RM0319 278/368 Doc ID 022640 Rev 3 24.4.5 RAM palette The RAM-based palette is a 256 x 16-bit dual-port RAM physically structured as 128 x 32 bit. This allows two entries to be written into the palette from a single word write access. The least significant bit of the serialized pixel data is used to select between upper and lower halves of the palette RAM. Which half is selected depends on the bytes ordering mode. In little-endian mode, the LSB being set selects the upper half, but in big-endian, the lower half of the palette is selected. WinCE byte ordering is little-endian, so the former case applies. Pixel data values can be written and verified through the AMBA AHB slave interface. For information on the numbers of colors supported, refer to Section 24.2: Main features. [24] 0 p1 - Green3 p1 - Blue0 [23] p0 - Blue7 p1 - Green2 p1 - Green3 [22] p0 - Blue6 p1 - Green1 p1 - Green2 [21] p0 - Blue5 p1 - Green0 p1 - Green1 [20] p0 - Blue4 p1 - Red4 p1 - Green0 [19] p0 - Blue3 p1 - Red3 p1 - Red3 [18] p0 - Blue2 p1 - Red2 p1 - Red2 [17] p0 - Blue1 p1 - Red1 p1 - Red1 [16] p0 - Blue0 p1 - Red0 p1 - Red0 [15] p0 - Green7 p0- Intensity bit 0 [14] p0 - Green6 p0 - Blue4 0 [13] p0 - Green5 p0 - Blue3 0 [12] p0 - Green4 p0 - Blue2 0 [11] p0 - Green3 p0 - Blue1 p0 - Blue3 [10] p0 - Green2 p0 - Blue0 p0 - Blue2 [09] p0 - Green1 p0 - Green4 p0 - Blue1 [08] p0 - Green0 p0 - Green3 p0 - Blue0 [07] p0 - Red7 p0 - Green2 p0 - Green3 [06] p0 - Red6 p0 - Green1 p0 - Green2 [05] p0 - Red5 p0 - Green0 p0 - Green1 [04] p0 - Red4 p0 - Red4 p0 - Green0 [03] p0 - Red3 p0 - Red3 p0 - Red3 [02] p0 - Red2 p0 - Red2 p0 - Red2 [01] p0 - Red1 p0 - Red1 p0 - Red1 [00] p0 - Red0 p0 - Red0 p0 - Red0 Table 84. RGB mode data format (continued) DMA FIFO output bit 24-bit RGB 16-bit 1:5:5:5 RGB 16-bit 4:4:4 RGB |
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