RM0319 datasheet(263/368 Pages) STMICROELECTRONICS

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RM0319

Basic general purpose I/Os (basGPIO)

Doc ID 022640 Rev 3

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22.3.3

Mode control

Each GPIO line can be controlled by software.

The data direction is controlled by the data direction register (GPIODIR). Data writing and

reading operations are detailed in the next section.

22.4

Programming examples

22.4.1

How to read from and write to input/output lines

To allow independent software drivers to set their GPIO bits without affecting any other pins

in a single write operation, the APB address bus (PADDR) is used as a mask on read/write

operations.

The GPIO data register (GPIODATA) effectively covers 64 locations in the address space,

that is the same register appears at 64 different locations (with offset ranging from 0x00 to

0xFC with respect to base address). To access these locations, the 6 bit subset of the APB

address bus is used, according to the following rules:

●

During a write operation to GPIODATA register: a data bit of the GPIODATA register is

altered only if the associated address bit in PADDR[9:2] is set, otherwise it is left

unchanged.

●

During a read operation from GPIODATA register: a data bit of the GPIODATA register

is read only if the associated address bit in PADDR[9:2] is set, otherwise a zero is

returned regardless of its state.

22.4.2

Control interrupt generation

The GPIO interrupt generation capability is fully controlled by a set of seven registers

located in the APB slave interface.

These registers allow to select, for each single pin, the interrupt source (the edge or the

level of signal on that pin), the event (rising/falling edge or high/low signal level) which

triggers the interrupt and any interrupt masking.

Figure 94 shows how the three main interrupt control registers (namely GPIOIS, GPIOIBE

and GPIOIEV) should be set to select an interrupt source event for a single pin.

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