RM0319 datasheet(259/368 Pages) STMICROELECTRONICS

259 / 368 page

RM0319

Analog-to-digital converter (ADC)

Doc ID 022640 Rev 3

259/368

21.3.1

Operation modes

Normal mode

As long as POWER DOWN bit in ADC_STATUS_REG register is set to logic ’0’, the ADC is

inactive (disabled) and the output latches contain the last conversion.

When the POWER DOWN bit is set by software, the ADC enters its functional mode after 50

µs, when a conversion can be then initiated by setting the ENABLE bit in

ADC_STATUS_REG register.

At first, the 10-bit conversion data field of the AVERAGE_REG register is reset to the value

10'b1000000000 and the acquisition from the selected analog input channel occurs. After

that, the conversion phase takes place. 13 clock cycles are required for one complete

conversion.

At the end of conversion, the CONVERSION READY bit in ADC_STATUS_REG is set, and

the conversion data reading can begin. When the reading finishes, two different scenarios

could occur:

●

POWER DOWN bit is set (1'b1): the ENABLE bit is kept to 1'b1 (conversion enabled),

and next conversion can takes place without waiting for the start up time (50 us).

●

POWER DOWN bit is cleared (1'b0): the ADC is switched-off and next conversion

requires again a start up time (after setting the ENABLE bit in the ADC_STATUS_REG

21.3.2

Enhanced mode

In this mode (ENHANCED MODE bit = 1), it is possible to perform conversions on selected

channels in a continuous way. To start conversions it is necessary to configure the

SCAN_RATE register to set the number of APB Clock cycles between the start of two scan

conversions.

To read conversion results you need to read the CHx_DATA registers. CHx_DATA[17] is the

VALID_DATA bit. It is logic ‘1’ when the read data is valid. It is logic ‘0’ in the following cases:

●

ENHANCED MODE bit = 0

●

CHANNEL ENABLE of the related channel = 0

●

The controller is writing a result in it.

On channel 0 it is possible to select a request to DMA (DMA_EN bit = 1) when conversion is

finished. In this case at the end of conversion on this channel, the controller will perform a

single request to DMA. At the next conversion on channel 0, the controller will check for the

end of last DMA transfer continuing with a new conversion on this channel only if the first

one is finished. Otherwise, the scan will continue with the other enabled channels.

21.3.3

High-resolution mode

The resolution of the ADC analog cell is 10 bits, but resolution can be extended in high

resolution mode. High resolution mode is enabled by setting the HIGHRESOLUTION bit in

the ADC_CTRL_STATUS _REG register.

In high resolution mode, the ADC performs oversampling. The number of samples is

programmable via the NSAMPLES bits (bits 7:5) in the ADC_CTRL_STATUS _REG

The sum of the converted results can be read from the AVERAGE register.

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