RM0319 datasheet(220/368 Pages) STMICROELECTRONICS

220 / 368 page

Asynchronous serial ports (UART)

RM0319

220/368

Doc ID 022640 Rev 3

16.3.3

Baud Rate Generator

The Baud Rate Generator contains free-running counters that generate the internal x16

clocks, and Baud16 signal.

Baud16 provides timing information for UART transmit and receive control. It consists of a

stream of pulses with a width of one UARTCLK clock period and a frequency of 16 times the

baud rate.

16.3.4

Transmit FIFO

The transmit FIFO consists of an 8-bit wide, 16 location deep, and FIFO memory buffer.

CPU data written across the APB interface is stored in this FIFO until read out by the

Transmit LogicThe Receive FIFO block can be disabled to act like a one-byte holding

Note:

The Transmit FIFO block can be disabled to act like a one-byte holding register.

16.3.5

Receive FIFO

The receive FIFO consists of a 12-bit wide, 16 locations deep FIFO memory buffer.

Received data and corresponding error bits are stored in the Receive FIFO by the Receive

Logic until read out by the CPU across the APB interface. This block can be disabled to act

like a one-byte holding register.

Note:

The Receive FIFO block can be disabled to act like a one-byte holding register.

16.3.6

Transmit Logic

The transmit logic performs parallel-to-serial conversion on the data read from the Transmit

FIFO. The control logic outputs the serial bit stream beginning with a start bit followed by

data bits, with the LSB first and ended by parity bit and stop bit according to the

programmed configuration in control registers.

16.3.7

Receive logic

The receive logic performs serial-to-parallel conversion on the received serial bit stream

after a valid pulse has been detected. The Receive Logic also performs detection of

overrun, parity, frame error checking and line break, and their status accompanies the data

that is written to the Receive FIFO.

16.3.8

DMA interface

The UART provides a DMA Interface to connect to a DMA controller. The DMA operation of

the UART is controlled through the UART DMA control register.

The burst transfer and single transfer request signals are not mutually exclusive, so they can

both be asserted at the same time. When the UART is in the FIFO disabled mode (where

both FIFO’s act like a one-byte holding register), only the DMA single transfer mode can

operate, since only one character can be transferred to or from the FIFO at any time.

16.3.9

Synchronization registers and logic

Since the UART supports both asynchronous and synchronous operation of the clocks

PCLK and UARTCLK, Synchronization Registers and Handshaking Logic have been

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