RM0319 datasheet(205/368 Pages) STMICROELECTRONICS

205 / 368 page

RM0319

Controller area network ports (CAN)

Doc ID 022640 Rev 3

205/368

15.4.15

Configuring a FIFO buffer

With the exception of the EoB bit, the configuration of receive objects belonging to a FIFO

Buffer is the same as the configuration of a (single) receive object, see Section 15.4.13

To concatenate two or more message objects into a FIFO buffer, the identifiers and masks

of these message objects (if used) have to be programmed to matching values. Due to the

implicit priority of the message objects, the message object with the lowest number will be

the first message object of the FIFO Buffer. The EoB bit of all message objects of a FIFO

Buffer except the last have to be programmed to zero. The EoB bits of the last message

object of a FIFO Buffer is set to one, configuring it as the end of the block.

15.4.16

Receiving messages with FIFO buffers

Received messages with identifiers matching to a FIFO buffer are stored into a message

object of this FIFO buffer starting with the message object with the lowest message number.

When a message is stored into a message object of a FIFO buffer the NewDat bit of this

message object is set. By setting NewDat while EoB is zero the message object is locked for

further write accesses by the message handler until the CPU has written the NewDat bit

back to zero.

Messages are stored into a FIFO buffer until the last message object of this FIFO buffer is

reached. If none of the preceding message objects is released by writing NewDat to zero, all

further messages for this FIFO buffer will be written into the last message object of the FIFO

Buffer and therefore overwrite previous message.

15.4.17

Reading from a FIFO buffer

When the CPU transfers the contents of message object to the IFx Message Bugger

registers by writing its number to the IFx Command Request register, the corresponding

Command Mask register should be programmed the way that bits NewDat and IntPnd are

reset to zero (TxRqst/NewDat = ‘1’ and ClrIntPnd = ‘1’). The values of these bits in the

Message Control register always reflect the status before resetting the bits.

To assure the correct function of a FIFO Buffer, the CPU should read out the message

objects starting at the FIFO Object with the lowest message number.

Figure 73 shows how a set of message objects which are concatenated to a FIFO Buffer

can be handled by the CPU.

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