RM0319 datasheet(178/368 Pages) STMICROELECTRONICS

178 / 368 page

Fast Ethernet ports (RMII0/RMII1/MII1)

RM0319

178/368

Doc ID 022640 Rev 3

13.6.7

Transmitting frames in MII/RMII mode

To set up a frame for transmission:

Enable transmit in the network control register.

Allocate an area of system memory for transmit data. This does not have to be

contiguous, varying byte lengths can be used as long as they conclude on byte

borders.

Set-up the transmit buffer list.

Set the network control register to enable transmission and enable interrupts.

Write data for transmission into these buffers.

Write the address to transmit buffer descriptor queue pointer.

Write control and length to word one of the transmit buffer descriptor entry.

Write to the transmit start bit in the network control register.

13.6.8

Receiving frames in MII/RMII mode

When a frame is received and the receive circuits are enabled, the MACB checks the

address and, in the following cases, the frame is written to system memory:

If it matches one of the four specific address registers.

If it matches the hash address function.

If it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed.

If the MACB is configured to copy all frames.

If the EAM is asserted before four words have been loaded into the receive FIFO.

The register receive buffer queue pointer points to the next descriptor entry (see Receive

Buffer Descriptor Entry) and the MACB uses this as the address in system memory to write

the frame to. Once the frame has been completely and successfully received and written to

system memory, the MACB then updates the receive buffer descriptor entry with the reason

for the address match and marks the area as being owned by software. Once this is

complete an interrupt receive complete is set. Software is then responsible for handling the

data in the buffer and then releasing the buffer by writing the ownership bit back to 0. If the

MACB is unable to write the data at a rate to match the incoming frame, then an interrupt

receive overrun is set. If there is no receive buffer available, that is. the next buffer is still

owned by software, the interrupt receive buffer not available is set. If the frame is not

successfully received, a statistic register is incremented and the frame is discarded without

informing software.

RM0319 датащи(PDF) 178 Page - STMicroelectronics