RM0319 datasheet(177/368 Pages) STMICROELECTRONICS

177 / 368 page

RM0319

Fast Ethernet ports (RMII0/RMII1/MII1)

Doc ID 022640 Rev 3

177/368

Figure 55.

Transmit buffer list

13.6.6

Using the PHY maintenance register

The PHY maintenance register enables the MACB to communicate with a PHY by means of

the MDIO interface. It is used during auto-negotiation to ensure that the MACB and the PHY

are configured for the same speed and duplex configuration.

The PHY maintenance register is implemented as a shift register. Writing to the register

starts a shift operation which is signalled as complete when bit two is set in the network

status register (about 2000 pclk cycles later when bits ten and eleven are set to 10 in the

network configuration register). An interrupt is generated as this bit is set. During this time,

the MSB of the PHY maintenance register is output on the mdio_out pin and the LSB

updated from the mdio_in pin with each mdc cycle. This causes the transmission of a PHY

management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 Standard.

Reading during the shift operation will return the current contents of the shift register. At the

end of the management operation the bits will have shifted back to their original locations.

For a read operation the data bits will be updated with data read from the PHY. It is

important to write the correct values to the register to ensure a valid PHY management

frame is produced. mdc should not toggle faster than 2.5 MHz (minimum period of 400 ns).

mdc is generated by dividing down pclk. Three bits in the network configuration register

determine by how much pclk should be divided to produce mdc. The default is 32 which is

acceptable for pclk running up to 80 MHz.

At the chip level mdio_out, mdio_en and mdio_in connect to a single tri-state I/O buffer

called MDIO. Alternatively MDIO may be implemented as a pull-down. In this case the

enable to the pull-down should be driven with ~mdio_out and mdio_en.

Destination Address

(In frame)

Specific Address 1

Specific Address 2

Specific Address 3

Specific Address 4

match 1

match 2

match 3

match 4

match hash

Hash Address Reg(MAC)

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