RM0319 datasheet(176/368 Pages) STMICROELECTRONICS

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Fast Ethernet ports (RMII0/RMII1/MII1)

RM0319

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Doc ID 022640 Rev 3

To create this list of buffers:

Allocate a number (n) of buffers of 128 bytes in system memory.

Allocate an area of 2n words for the receive buffer descriptor entry in system memory

and create n entries in this list. Mark all entries in this list as owned by MACB, which

means that the bit 0 of word 0 should be set to 0.

If less than 1024 buffers are defined, the last descriptor must be marked with the wrap

bit (bit 1 in word 0 set to 1).

Write address of receive buffer descriptor entry to MACB register receive_buffer queue

pointer.

The receive circuits can then be enabled by writing to the address recognition registers

and then to the network control register.

13.6.5

Creating a transmit buffer list

Transmit data is read from areas of data (buffers) in the system memory. These buffers are

listed in another data structure that also resides in the main memory. This data structure

(transmit buffer queue) is a sequence of descriptor entries as defined in the transmit buffer

descriptor entry. It points to this data structure.

To create this list of buffers:

Allocate a number (n) of buffers of between 1 and 2047 bytes of data to be transmitted

in system memory. Up to 128 buffers per frame are allowed.

Allocate an area 2n words for the transmit buffer descriptor entry in system memory

and create N entries in this list. Mark all entries in this list as owned by MACB, i.e. bit 31

of word 1 set to 0.

If fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap

bit (bit 30 in word 1) set to 1.

Write address of transmit buffer descriptor entry to MACB register transmit_buffer

queue pointer.

The transmit circuits can then be enabled by writing to the network control register.

The MACB register-pair hash address and the four specific address register pairs must be

written with the required values. Each register pair comprises of a bottom register and top

particular register pair after the bottom-register has been written and re-enabled when the

top register is written. See the Address checking block for details of address matching. Each

enabled or disabled.

RM0319 датащи(PDF) 176 Page - STMicroelectronics