RM0319 datasheet(114/368 Pages) STMICROELECTRONICS

114 / 368 page

USB 2.0 Host ports (UHC)

RM0319

114/368

Doc ID 022640 Rev 3

endpoint data from the system memory, after reading every DWORD from the application’s

FIFO it splits the DWORD into 4 individual bytes and then sends it to the DFIFO. It also

implements byte-alignment logic, that is when a write cycle is initiated by FML block at the

odd boundary (not the DWORD boundary), it reads only the lower 2 bit of the address (ties

them to 0), so that the application always writes at DWORD boundary, and manipulates the

byte-enables accordingly.

HCI slave block

The HCI slave block is the slave on HCI bus. This is basically an interface between OHCI

operational register internal to the Host Controller and the application. It updates the

registers on writes and provides the register data on reads. All the slave accesses should be

DWORD aligned. Therefore, byte enables are not used in slave accesses.

List processor block

The list processor block acts as a main controller of the entire controller. It has multiple state

machines to implement List Service Flow, List Priority, USB-States, ED, TD Service,

StatusWriteBack, TD Retirement, and so on as per the OHCI specification. Additionally, this

block implements a controller which interfaces with HCI_master and hsie, helping them in

the data transfer from system memory to USB and USB to system memory.

The following submodules are included:

●

USB states

●

List service flow

●

ED-TD block

●

HCI master interface logic

●

Data read write logic

RootHub and HSIE blocks

Since implementation varies, most of the functionality of the RootHub is implemented in the

Port Configuration Block. This logic is common to any user configuration. The logic in this

block acts as a wrapper around HSIE and interface with Host Controller’s List Processor,

FIFO and OHCI registers. This block also implements the control logic to synchronize the

interface between HSIE and port S/M.

This block implements the following submodules:

●

Reset_Resume

●

DPLL

●

HSIE

Digital PLL block (DPLL)

The function of the DPLL Block is to extract the clock and data information from the USB

Data received from the different transceiver. The Digital PLL runs on a 48 MHz user-

provided clock to extract the clock information from the USB for both Full-Speed and Low-

speed data. The two signals D+ and D- of the USB lines are passed through a differential

receiver (external to the UHOSTC controller) and a NRZI formatted data is obtained from

the output of the differential receivers. The output of the differential receiver is then used by

the Digital PLL to extract clock information. The PLL Block also has a SE0 Detect Logic to

detect the Single Ended Zero (SE0) in the data stream. The circuit in this module extracts

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