RM0319 datasheet(111/368 Pages) STMICROELECTRONICS

111 / 368 page

RM0319

USB 2.0 Host ports (UHC)

Doc ID 022640 Rev 3

111/368

10.3

Functional description

Figure 31.

UHC block diagram.

10.3.1

AHB bus interface unit (BIU)

USB 2.0 Host access to the AHB bus is granted by the AHB Bus Interface Unit (BIU), which

consists of a master module and a slave module.

The AHB BIU Slave module acts a slave on the AHB and responds to all EHCI/OHCI

operational registers (see Operational registers on page 112) accesses from an AHB

master. In particular, this module allows RW access to its operational registers through the

AHB bus.

Note:

There is only a single AHB slave port in AHB BIU Slave module for both EHCI and OHCI

host controller registers access.

The AHB BIU Master module, acting as a master on the AHB, receives requests from the

List Processor block (see List processor on page 112) within the EHCI Host Controller, and

transfers data with system memory through the AHB bus. The AHB BIU Master supports 8-,

16-, and 32 bit data transfers, and 32 bit address transfers.

10.3.2

EHCI host controller

An EHCI Host Controller compliant with the EHCI specification (version 1.0) is embedded

within the UHC to support the 480 Mbps high-speed (HS) transaction of USB 2.0. HS

devices connected to the two downstream ports.

The main blocks of the EHCI host controller are described below.

EHCI

OHCI

SOF

Generator

EHCI

Operation

List

Processor

Packet Buffer

Port0

Port1

USB2.0 EHCI Controller

USB1.1 OHCI

Controller

USB1.1 OHCI

Controller

UHC

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