PM0056 datasheet(127/156 Pages) STMICROELECTRONICS

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PM0056

Core peripherals

A pending interrupt remains pending until one of the following:

•

The processor enters the ISR for the interrupt. This changes the state of the interrupt

from pending to active. Then:

–

For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC

samples the interrupt signal. If the signal is asserted, the state of the interrupt

changes to pending, which might cause the processor to immediately re-enter the

ISR. Otherwise, the state of the interrupt changes to inactive.

–

For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this

is pulsed the state of the interrupt changes to pending and active. In this case,

when the processor returns from the ISR the state of the interrupt changes to

pending, which might cause the processor to immediately re-enter the ISR. If the

interrupt signal is not pulsed while the processor is in the ISR, when the processor

returns from the ISR the state of the interrupt changes to inactive.

•

Software writes to the corresponding interrupt clear-pending register bit.

For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the

interrupt does not change. Otherwise, the state of the interrupt changes to inactive.

For a pulse interrupt, state of the interrupt changes to:

–

Inactive, if the state was pending

–

Active, if the state was active and pending.

4.3.10

NVIC design hints and tips

Ensure software uses correctly aligned register accesses. The processor does not support

unaligned accesses to NVIC registers. See the individual register descriptions for the

supported access sizes.

A interrupt can enter pending state even it is disabled.

Before programming VTOR to relocate the vector table, ensure the vector table entries of

the new vector table are setup for fault handlers, NMI and all enabled exception like

interrupts. For more information see Section 4.4.4: Vector table offset register (SCB_VTOR)

on page 133.

NVIC programming hints

Software uses the CPSIE I and CPSID I instructions to enable and disable interrupts. The

CMSIS provides the following intrinsic functions for these instructions:

void __disable_irq(void) // Disable Interrupts

void __enable_irq(void) // Enable Interrupts

In addition, the CMSIS provides a number of functions for NVIC control, including:

Table 43. CMSIS functions for NVIC control

CMSIS interrupt control function

Description

void NVIC_SetPriorityGrouping(uint32_t priority_grouping) Set the priority grouping

void NVIC_EnableIRQ(IRQn_t IRQn)

Enable IRQn

void NVIC_DisableIRQ(IRQn_t IRQn)

Disable IRQn

uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)

Return true (IRQ-Number) if IRQn is

pending

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