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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PM0056 датащи(PDF) 107 Page - STMicroelectronics |
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PM0056 датащи(HTML) 107 Page - STMicroelectronics |
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107 / 156 page  DocID15491 Rev 5 107/156 PM0056 Core peripherals Table 36 shows the cache policy for memory attribute encodings with a TEX value is in the range 4-7. Table 37 shows the AP encodings that define the access permissions for privileged and unprivileged software. Table 35. TEX, C, B, and S encoding TEX C B S Memory type Shareability Other attributes b000 0 0x (1) Strongly-ordered Shareable - 1 x(1) Device Shareable - 1 0 0 Normal Not shareable Outer and inner write-through. No write allocate. 1 Shareable 1 0 Normal Not shareable Outer and inner write-back. No write allocate. 1 Shareable b001 0 00 Normal Not shareable Outer and inner Non-cacheable. 1 Shareable 1 x(1) Reserved encoding - 1 0 x(1) Implementation defined attributes. - 1 0 Normal Not shareable Outer and inner write-back. Write and read allocate. 1 Shareable b010 0 0 x(1) Device Not shareable Non-shared Device. 1 x(1) Reserved encoding - 1x(1) x(1) Reserved encoding - b1BB A A 0 Normal Not shareable Cached memory(2), BB = outer policy, AA = inner policy. 1 Shareable 1. THe MPU ignores the value for this bit. 2. See Table 36 for the encoding of the AA and BB bits. Table 36. Cache policy for memory attribute encoding Encoding, AA or BB Corresponding cache policy 00 Non-cacheable 01 Write back, write and read allocate 10 Write through, no write allocate 11 Write back, no write allocate |
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