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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M68ICS08GR датащи(PDF) 120 Page - Freescale Semiconductor, Inc |
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M68ICS08GR датащи(HTML) 120 Page - Freescale Semiconductor, Inc |
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120 / 408 page  Clock Generator Module (CGMC) Technical Data MC68HC908GR8 — Rev 4.0 120 Clock Generator Module (CGMC) MOTOROLA NOTE: The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). PMSH[7:4] — Unimplemented Bits These bits have no function and always read as logic 0s. 7.6.4 PLL Multiplier Select Register Low The PLL multiplier select register low (PMSL) contains the programming information for the low byte of the modulo feedback divider. MUL7–MUL0 — Multiplier Select Bits These read/write bits control the low byte of the modulo feedback divider that selects the VCO frequency multiplier, N. (See PLL Circuits and Programming the PLL.) MUL7–MUL0 cannot be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to $40 for a default multiply value of 64. NOTE: The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). Address: $0038 Bit 7 654321 Bit 0 Read: MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0 Write: Reset: 01000000 Figure 7-7. PLL Multiplier Select Register Low (PMSL) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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